參數(shù)資料
型號: HY57V281620HCST-SI
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 4 Banks x 2M x 16bits Synchronous DRAM
中文描述: 8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝: 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
文件頁數(shù): 8/11頁
文件大?。?/td> 79K
代理商: HY57V281620HCST-SI
HY57V281620HC(L/S)T-I
Rev. 1.0/Mar. 02
8
AC CHARACTERISTICS II
Note :
1. A new command can be given tRRC after self refresh exit
Parameter
Symbol
-6I
-7I
-KI
-HI
-8I
-PI
-SI
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
RAS Cycle Time
Operation
tRC
60
-
60
-
60
-
65
-
68
-
70
-
70
-
ns
Auto Refresh
tRRC
60
-
65
-
65
-
65
-
68
-
70
-
70
-
ns
RAS to CAS Delay
tRCD
18
-
20
-
15
-
20
-
20
-
20
-
20
-
ns
RAS Active Time
tRAS
42
100K
45
100K
45
100K
45
100K
48
100K
50
100K
50
100K
ns
RAS Precharge Time
tRP
18
-
20
-
15
-
20
-
20
-
20
-
20
-
ns
RAS to RAS Bank Active Delay
tRRD
12
-
14
-
15
-
15
-
16
-
20
-
20
-
ns
CAS to CAS Delay
tCCD
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Write Command to Data-In Delay
tWTL
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
Data-In to Precharge Command
tDPL
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
Data-In to Active Command
tDAL
5
-
5
-
4
-
5
-
4
-
3
-
3
-
CLK
DQM to Data-Out Hi-Z
tDQZ
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
DQM to Data-In Mask
tDQM
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
MRS to New Command
tMRD
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
Precharge to Data
Output Hi-Z
CAS Latency = 3
tPROZ3
3
-
3
-
3
-
3
-
3
-
3
-
3
-
CLK
CAS Latency = 2
tPROZ2
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
Power Down Exit Time
tPDE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Self Refresh Exit Time
tSRE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
1
Refresh Time
tREF
-
64
-
64
-
64
-
64
-
64
-
64
-
64
ms
相關(guān)PDF資料
PDF描述
HY57V283220(L)T(P)-H 4 Banks x 1M x 32Bit Synchronous DRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HY57V281620HCT 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620HCT-5 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM
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HY57V281620HCT-6I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM
HY57V281620HCT-7 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X2MX16|CMOS|TSOP|54PIN|PLASTIC