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參數(shù)資料
| 型號： | HY57V281620ETP-7 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
| 中文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-54 |
| 文件頁數(shù)： | 4/13頁 |
| 文件大小： | 126K |
| 代理商： | HY57V281620ETP-7 |
Rev. 1.1 / J an. 2005
4
Synchronous DRAM Memory 128Mbit (8Mx16bit)
HY57V281620E(L)T(P) Series
PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are registered to the SDRAM
on the rising edge of CLK
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among power down, suspend or self refresh
CS
Chip Select
Enables or disables all inputs except CLK, CKE, UDQM and LDQM
BA0, BA1
Bank Address
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11
Address
Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA8
Auto-precharge flag: A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
UDQM, LDQM
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write
mode
DQ0 ~ DQ15
Data Input/Output
Multiplexed data input / output pin
VDD/VSS
Power Supply/Ground
Power supply for internal circuits and input buffers
VDDQ/VSSQ
Data Output Power/Ground
Power supply for output buffers
NC
No Connection
No connection
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY57V281620ETP-H | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
| HY57V281620FTP-HDR-C | 制造商:SK Hynix Inc 功能描述: |
| HY57V281620FTP-HI-C | 制造商:SK Hynix Inc 功能描述: |
| HY57V281620FTP-HIDR-C | 制造商:SK Hynix Inc 功能描述: |
| HY57V281620HCLT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx16|3.3V|4K|6|SDR SDRAM - 128M |
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