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參數(shù)資料
| 型號： | HY57V281620ELT |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
| 中文描述： | 128Mb的同步DRAM的基礎上2米x 4Bank x16的I / O |
| 文件頁數(shù)： | 11/13頁 |
| 文件大小： | 126K |
| 代理商： | HY57V281620ELT |
Rev. 1.1 / J an. 2005
11
Synchronous DRAM Memory 128Mbit (8Mx16bit)
HY57V281620E(L)T(P) Series
AC CHARACTERISTICS II
(AC operating conditions unless otherwise noted)
Note: 1. A new command can be given t
RRC
after self refresh exit.
Parameter
Symbol
5
6
7
H
Unit Note
Min
Max
Min
Max
Min
Max
Min Max
RAS Cycle Time
Operation
t
RC
55
-
60
-
63
-
63
-
ns
RAS Cycle Time
Auto Refresh
t
RRC
55
-
60
-
63
-
63
-
ns
RAS to CAS Delay
t
RCD
15
-
18
-
20
-
20
-
ns
RAS Active Time
t
RAS
38.7 100K
42
100K
42
100K
42
120K
ns
RAS Precharge Time
t
RP
15
-
18
-
20
-
20
-
ns
RAS to RAS Bank Active Delay
t
RRD
10
-
12
-
14
-
15
-
ns
CAS to CAS Delay
t
CCD
1
-
1
-
1
-
1
-
CLK
Write Command to
Data-In Delay
t
WTL
0
-
0
-
0
-
0
-
CLK
Data-in to Precharge Command
t
DPL
2
-
2
-
2
-
2
-
CLK
Data-In to Active Command
t
DAL
t
DPL
+ t
RP
DQM to Data-Out Hi-Z
t
DQZ
2
-
2
-
2
-
2
-
CLK
DQM to Data-In Mask
t
DQM
0
-
0
-
0
-
0
-
CLK
MRS to New Command
t
MRD
2
-
2
-
2
-
2
-
CLK
Precharge to Data
Output High-Z
CAS
Latency=3
t
PROZ3
3
-
3
-
3
-
3
-
CLK
CAS
Latency=2
t
PROZ2
2
-
2
-
2
-
2
-
CLK
Power Down Exit Time
t
DPE
1
-
1
-
1
-
1
-
CLK
Self Refresh Exit Time
t
SRE
1
-
1
-
1
-
1
-
CLK
1
Refresh Time
t
REF
-
64
-
64
-
64
-
64
ms
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HY57V281620ELT-5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
| HY57V281620ELT-6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
| HY57V281620ELT-7 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
| HY57V281620ELT-H | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
| HY57V281620ELTP-5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
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