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參數(shù)資料
| 型號： | HY5756820C |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 4 Banks x 8M x 8Bit Synchronous DRAM |
| 中文描述： | 4銀行× 8米× 8位同步DRAM |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 89K |
| 代理商： | HY5756820C |
HY57V56820C(L)T
Rev. 0.4 / July 2003
11
COMMAND TRUTH TABLE
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don
′
t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
ADDR
A10/
AP
BA
Note
Mode Register Set
H
X
L
L
L
L
X
OP code
No Operation
H
X
H
X
X
X
X
X
L
H
H
H
Bank Active
H
X
L
L
H
H
X
RA
V
Read
H
X
L
H
L
H
X
CA
L
V
Read with Autoprecharge
H
Write
H
X
L
H
L
L
X
CA
L
V
Write with Autoprecharge
H
Precharge All Banks
H
X
L
L
H
L
X
X
H
X
Precharge selected Bank
L
V
Burst Stop
H
X
L
H
H
L
X
X
DQM
H
X
V
X
Auto Refresh
H
H
L
L
L
H
X
X
Burst-Read-Single-WRITE
H
X
L
L
L
H
X
A9 Pin High
(Other Pins OP code)
Self Refresh
1
Entry
H
L
L
L
L
H
X
X
Exit
L
H
H
X
X
X
X
L
H
H
H
Precharge
power down
Entry
H
L
H
X
X
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
X
L
H
H
H
Clock
Suspend
Entry
H
L
H
X
X
X
X
X
L
V
V
V
Exit
L
H
X
X
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| HY57V56820CLT-6 | 4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V56820CLT-8 | 4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V56820CLT-H | 4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V56820CLT-K | 4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V56820CLT-P | 4 Banks x 8M x 8Bit Synchronous DRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HY57V121620 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 8M x 16Bit Synchronous DRAM |
| HY57V121620LT | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 8M x 16Bit Synchronous DRAM |
| HY57V121620LT-6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 8M x 16Bit Synchronous DRAM |
| HY57V121620LT-8 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 8M x 16Bit Synchronous DRAM |
| HY57V121620LT-H | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 8M x 16Bit Synchronous DRAM |
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