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參數資料
| 型號： | HY27UF081G2M-TPCS |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| 中文描述： | 128M X 8 FLASH 3.3V PROM, 30 ns, PDSO48 |
| 封裝： | 12 X 20 MM, 1.20 MM HEIGHT, LEAD FREE, TSOP1-48 |
| 文件頁數： | 1/48頁 |
| 文件大?。?/td> | 476K |
| 代理商： | HY27UF081G2M-TPCS |
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Rev 0.7 / Apr. 2005
1
Preliminary
HY27UF(08/ 16)1G2M Series
HY27SF(08/ 16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Document Title
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
Revision History
Revision
No.
History
Draft Date
Remark
0.0
1) Initial Draft.
Aug. 2004
Preliminary
0.1
1) Correct Fig.10 Sequential out cycle after read
2) Add the text to Fig.1, Table.1, Table.2
- text : IO15 - IO8 (x16 only)
3) Delete ‘3.2 Page program NOTE 1.
- Note : if possible it is better to remove this constrain
4) Change the text ( page 10,13, 45)
- 2.2 Address Input : 28 Addresses -> 27 Addresses
- 3.7 Reset : Fig.29 -> Fig.30
- 5.1 Automatic page read after power up : Fig.30 -> Fig.29
5) Add 5.3 Addressing for program operation & Fig.34
1) Change TSOP, WSOP, FBGA package dimension & figures.
- Change TSOP, WSOP, FBGA package mechanical data
- Change FBGA thickness (1.2 -> 1.0 mm)
2) Correct TSOP, WSOP Pin configurations.
- 38th NC pin has been changed Lockpre
(figure 3,4)
3) Edit figure 15,19 & table 4
4) Add Bad Block Management
5) Change Device Identifier 3rd Byte
- 3rd Byte ID is changed. (reserved -> don't care)
- 3rd Byte ID table is deleted.
1) Add Errata
Sep. 2004
Preliminary
0.2
Oct. 2004
Preliminary
0.3
2) LOCKPRE is changed to PRE.
- Texts, Table, Figures are changed.
3) Add Note.4 (table.14)
4) Block Lock Mechanism is deleted.
- Texts, Table, figures are deleted.
5) Add Application Note(Power-On/Off Sequence & Auto Sleep mode.)
- Texts & Figures are added.
6) Edit the figures. (#10~25)
1) Change AC characteristics(tREH)
before: 20ns -> after: 30ns
2) Edit Note.1 (page. 21)
3) Edit the Application note 1,2
4) Edit The Address cycle map (x8, x16)
Nov.29 2004
Preliminary
0.4
Jan.19 2005
Preliminary
tCLS
tCLH
tWP
tALS
tALH
tDS
tWC
tR
Specification
0
10
25
0
10
20
50
25
Relaxed value
5
15
40
5
15
25
60
27
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HY27UF081G2M-TPEB | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| HY27UF081G2M-TPEP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| HY27UF081G2M-TPES | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| HY27UF081G2M-TPIB | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| HY27UF081G2M-TPIP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
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