
Rev 0.7 / Apr. 2005
25
Preliminary
HY27UF(08/ 16)1G2M Series
HY27SF(08/ 16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
W:&
W$/6
W&/+
W&+
W:3
W:+
W'+
',1
',1
',1ILQDO
W:+
W'+
W'+
W'6
W'6
W'6
W:3
W:3
&/(
$/(
&(
,2[
:(
Figure 10: Sequential Out Cycle after Read (CLE= L, WE#= H, ALE= L)
W
&($
W
5($
W
53
W
5($
W
5+=
W
5+=
W
2+
'RXW
'RXW
'RXW
W
&+=
W
2+
W
5($
W
5(+
W
5&
W
55
127(67UDQVLWLRQLVPHDVXUHGP9IURPVWHDG\VWDWHYROWDJH
7KLVSDUDPHWHULVVDPSOHGDQGQRWWHVWHG
ZLWKORDG
&(
5(
5%
,2[
Figure 9. Input Data Latch Cycle