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參數(shù)資料
| 型號： | HY27LF081G2M-TIS |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| 中文描述： | 1Gbit的（128Mx8bit / 64Mx16bit）NAND閃存 |
| 文件頁數(shù)： | 12/48頁 |
| 文件大?。?/td> | 476K |
| 代理商： | HY27LF081G2M-TIS |
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Rev 0.7 / Apr. 2005
12
Preliminary
HY27UF(08/ 16)1G2M Series
HY27SF(08/ 16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
3. DEVICE OPERATION
3.1 Page Read.
Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h
to the command register along with four address cycles. In two consecutive read operations, the second one doesn’t’
need 00h command, which four address cycles and 30h command initiates that operation. Two types of operations are
available : random read, serial page read. The random read mode is enabled when the page address is changed. The
2112 bytes (X8 device) or 1056 words (X16 device) of data within the selected page are transferred to the data regis-
ters in less than 27us
(1)
(tR). The system controller may detect the completion of this data transfer (tR) by analyzing
the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 60ns
(1)
cycle
time by sequentially pulsing RE#. The repetitive high to low transitions of the RE# clock make the device output the
data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data out-
put command.
The column address of next data, which is going to be out, may be changed to the address which follows random data
output command.
Random data output can be operated multiple times regardless of how many times it is done in a page.
3.2 Page Program.
The device is programmed basically by page, but it does allow multiple partial page programming of a word or consec-
utive bytes up to 2112 (X8 device) or words up to 1056 (X16 device), in a single page program cycle. The number of
consecutive partial page programming operation within the same page without an intervening erase operation must
not exceed 4 times for main array (X8 device:1time/512byte, X16 device:1time/256word) and 4 times for spare array
(X8 device:1time/16byte ,X16 device:1time/8word).
The addressing should be done in sequential order in a block
1
.
A page program cycle consists of a serial data
loading period in which up to 2112bytes (X8 device) or 1056words (X16 device) of data may be loaded into the data
register followed by a non-volatile programming period where the loaded data is programmed into the appropriate
cell.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the four cycle
address inputs and then serial data. The words other than those to be programmed do not need to be loaded. The
device supports random data input in a page. The column address of next data, which will be entered, may be
changed to the address which follows random data input command (85h). Random data input may be operated multi-
ple times regardless of how many times it is done in a page.
The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without previously
entering the serial data will not initiate the programming process. The internal write state controller automatically exe-
cutes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other
tasks. Once the program process starts, the Read Status Register command may be entered to read the status register.
The system controller can detect the completion of a program cycle by monitoring the RB# output, or the Status bit (I/
O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in
progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The internal write verify
detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Sta-
tus command mode until another valid command is written to the command register. Figure 15 details the sequence.
NOTE:
1. These parameters are applied to the errata.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY27LF081G2M-TMB | 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| HY27LF081G2M-TMP | 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| HY27LF081G2M-TMS | 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| HY27LF081G2M-TPCB | 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| HY27LF081G2M-TPCP | 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY27LF081G2M-TMB | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| HY27LF081G2M-TMP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| HY27LF081G2M-TMS | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| HY27LF081G2M-TPCB | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| HY27LF081G2M-TPCP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
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