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參數(shù)資料
| 型號： | HX6218DBHT |
| 英文描述： | x18 Synchronous FIFO |
| 中文描述： | x18同步FIFO |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 156K |
| 代理商： | HX6218DBHT |
7
HX6409/HX6218/HX6136
AC TIMING CHARACTERISTICS (1)
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and
output timing reference levels shown in the Tester AC Timing characteristics Table, capacitive output loading C
L
=50 pF. For C
L
>50 pF,
derate access times by 0.02 ns/pF (typical).
(2) Worst case operating conditions: VDD=4.5V to 5.5V, TC= -55
°
C to +125
°
C, post total dose at 25
°
C.
(3) For flag updates, tskew1 is the minimum time an opposite clock can occur after a clock and still not be included in the current clock cycle.
At less that tskew1, inclusion of the opposite clock is arbitrary.
(4) For flag updates, tskew2 is the minimum time an opposite clock can occur before a clock and still be included in the current clock cycle. At
less than tskew2, inclusion of the opposite clock is arbitrary.
(5) Timing parameters are defined in Figures 1 through 6.
Worst Cast (2)
—55C to 125°C
Symbol
Test Parameter
Min
Max
Units
TCKW
Write Clock Cycle
24
—
ns
TCKR
Read Clock Cycle
34
—
ns
TCKH
Clock High Read
24
—
ns
TCKH
Clock High Write
14
—
ns
TCKL
Clock Low
10
—
ns
TA
Data Access Time
—
30
ns
TOH
Previous Output Data Hold After Rd High
2
—
ns
TFH
Previous Flag Hold After Rd/Wr High
2
—
ns
TSD
Data Set-UP
9
—
ns
THD
Data Hold
4
—
ns
TSEN
Enable Set-UP
8
—
ns
THEN
Enable Hold
2
—
ns
TOE
OE Low to Output Data Valid
—
10
ns
TOLZ
OE Low to Output Data in Low Z
1
—
ns
TOHZ
OE High to Output Data in High Z
—
10
ns
TFD
Flag Delay
—
17
ns
TSKEW1
Opposite Clock after Clock (3)
0
—
ns
TSKEW2
Opposite Clock before Clock (4)
25
—
ns
TPMR
Master Reset Pulse Width (Low)
25
—
ns
TSCMR
Last Valid Clock Low Set-up to Master Reset Low
0
—
ns
TOHMR
Data Hold from Master Reset Low
2
—
ns
TMRR
Master Reset Recovery
8
—
ns
TMRF
Master Reset High to Flags Valid
—
17
ns
TAMR
Master Reset High to Data Outputs Low
—
17
ns
TSMRP
Parity Program Mode—MR Low Set-up
34
—
ns
THMRP
Parity Program Mode—MR Low Hold
24
—
ns
TFTP
Parity Program Mode—Write HIGH to Read HIGH
34
—
ns
TAP
Parity Program Mode—Data Access Time
—
30
ns
TOHP
Parity Program Mode—Data Hold Time from MR HIGH
4
—
ns
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| HX6218DBRC | x18 Synchronous FIFO |
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相關代理商/技術參數(shù) |
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|---|---|
| HX6218DBNC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DBNT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DBRC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DBRT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DENC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
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