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參數(shù)資料
| 型號： | HX6136FBFT |
| 英文描述： | x36 Synchronous FIFO |
| 中文描述： | x36同步FIFO |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 156K |
| 代理商： | HX6136FBFT |
3
HX6409/HX6218/HX6136
Signal Name
D: 0 - 35
I/O
I
Description
Data Inputs: Data Inputs are written into the FIFO on the rising edge of CKW when
ENW
is active and the FIFO is not full.
Q: 0 - 35
O
Data Outputs: Data Outputs are read out of the FIFO memory and updated on the rising
edge of CKR when
ENR
is active and the FIFO is not Empty. The Data Outputs are in a
high impedance state if
OE
is not active.
ENW
I
Enable Write: An active low signal that enables the write of the Data Inputs on the CKW
rising edge (if FIFO is not full).
ENR
I
Enable Read: An active low signal that enables the read and update of the Data Outputs
on the CKR rising edge (if FIFO is not empty).
CKW
I
Write Clock: The rising edge clocks data into the FIFO when
ENW
is low (active). On the
rising edge, this signal also updates the Half Full, 3/4 Full, Full, and Full Fault Flags.
CKR
I
Read Clock: The rising edge clocks data out of the FIFO when
ENR
is low (active). On
the rising edge, this signal also updates the 1/4 Full, Empty, and Empty Fault Flags.
HF
O
Half Full Flag: Updated on the rising edge of CKW and indicating that the FIFO is greater
than half full.
E/ F
O
Empty or Full Flag: Empty is updated on the rising edge of CKR, and Full is updated on
the rising edge of CKW.
QF/TQF
O
1/4 Full or 3/4 Full Flag: 1/4 Full is updated on the rising edge of CKR, and 3/4 Full is
updated on the rising edge of CKW. 1/4 Full signifies 256 or less words in the 1K x 36
FIFO and 3/4 Full signifies 256 words or less until a full condition.
EF_Fault
O
Empty or Full Fault Flag: empty Fault is updated on the rising edge of CKR, and Full
Fault is updated on the rising edge of CKW. Empty Fault signifies a read to an already
empty FIFO, and Full Fault signifies a write to an already full FIFO. Once a fault condition
is detected, the Fault Flag remains latched until the empty or full condition is removed.
MR
I
Master Reset: Active low signal which, when active, resets device to empty condition.
OE
I
Output Enable: Active low signal which, when active, enables low impedance Data
Outputs, Q: 0 - 35.
SIGNAL DEFINITIONS
PROGRAMMABLE PARITY OPTIONS
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相關PDF資料 |
PDF描述 |
|---|---|
| HX6136FBHC | x36 Synchronous FIFO |
| HX6136FBHT | x36 Synchronous FIFO |
| HX6136FBNC | x36 Synchronous FIFO |
| HX6136FBNT | x36 Synchronous FIFO |
| HX6136FBRC | x36 Synchronous FIFO |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HX6218DBFC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DBFT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DBHC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DBHT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DBNC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
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