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參數(shù)資料
| 型號： | HWD2111 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Dual 105mW Headphone Amplifier with Digital Volume Control and Shutdown Mode |
| 中文描述： | 雙105mW耳機放大器，具有數(shù)字音量控制和關(guān)斷模式 |
| 文件頁數(shù)： | 11/19頁 |
| 文件大小： | 1038K |
| 代理商： | HWD2111 |
Typical Performance Characteristics
(Continued)
Power Supply Rejection Ratio
Power Supply Rejection Ratio
Frequency Response
Supply Current vs
Supply Voltage
Application Information
DIGITAL VOLUME CONTROL
The
HWD
21
11’s gain is controlled by the signals applied to the
CLOCK and UP/DN inputs. An external clock is required to
drive the CLOCK pin. At each rising edge of the clock signal,
the gain will either increase or decrease by a 3dB step
depending on the logic voltage level applied to the UP/DN
pin. A logic high voltage level applied to the UP/DN pin
causes the gain to increase by 3dB at each rising edge of the
clock signal. Conversely, a logic low voltage level applied to
the UP/DN pin causes the gain to decrease 3dB at each
rising edge of the clock signal. For both the CLOCK and
UP/DN inputs, the trigger point is 1.4V minimum for a logic
high level, and 0.4V maximum for a logic low level.
There are 16 discrete gain settings ranging from +12dB
maximum to 33dB minimum. Upon device power on, the
amplifier’s gain is set to a default value of 0dB. However,
when coming out of shutdown mode, the
HWD
21
11 will revert
back to its previous gain setting.
The
HWD
21
11’s CLOCK and UP/DN pins should be de-
bounced in order to avoid unwanted state changes during
transitions between V
IL
and V
IH
. This will ensure correct
operation of the digital volume control. A microcontroller or
microprocessor output is recommended to drive the CLOCK
and UP/DN pins.
FIGURE 2. Timing Diagram
11
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