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參數(shù)資料

型號：	HW-V5-ML523-UNI-G-J
廠商：	Xilinx Inc
文件頁數(shù)：	88/91頁
文件大小：	0K
描述：	EVALUATION PLATFORM VIRTEX-5
產(chǎn)品變化通告：	Development Systems Discontinuation 16/Jan/2012
標準包裝：	1
系列：	Virtex®-5 FXT/LXT
類型：	FPGA
適用于相關產(chǎn)品：	XC5VLX110T-FF1136
所含物品：	ML52x 平臺，線纜，小型閃存卡，文檔 - 不包括電源 -

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics

DS202 (v5.3) May 5, 2010

www.xilinx.com

Product Specification

06/26/07

3.3

Added conditions to DVPPIN in Table 28, page 14.

Changed the FGTXMAX symbol name to FGTPMAX.

Updated GTP maximum line rates to 3.75 Gb/s in Table 30, page 16.

Updated maximum frequencies in Table33, page17.

Added 3.75 Gb/s condition and changed maximum value of FGTX in Table 34, page 17.

Added 3.75 Gb/s sinusoidal jitter specification and changed maximum value of FGRX in Table 35,

page 18.

Changed analog input common mode ranges in Table 51, page 26.

Changed TPKGSKEW values in Table99, page84.

07/26/07

3.4

Added maximum value of IREF to Table 3, page 2.

Revised Table 54 and changed the design software version in Table 55 for production devices.

In Table 64, page 44, added High Performance Mode to Note 2.

In Table 70, page 51, revised description of TSMDCCK/TSMCCKD.

Added Note 4 to TDUTYCYCRANGE_200_400 frequency range in Table 78, page 59.

In Virtex-5 Device Pin-to-Pin Input Parameter Guidelines: Revised note 1 in Table 91 through Table 96.

09/27/07

3.5

Added IBATT value and Note 2 to Table 3.

Added DRP Clock Frequency and Note 4 to Table 51. Revised the typical and maximum values and

units for gain error and bipolar gain error.

Removed unsupported XC5VSX95T -3 speed grade from Table 54 and Table 55.

Removed unsupported I/O standards (LVDS_33, LVDSEXT_33, and ULVDS_25) from Table 51. Also

updated LVDSEXT, 2.5V in Table 59.

Added values to Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK in

Table 70.

In Virtex-5 Device Pin-to-Pin Input Parameter Guidelines: Revised note 1 in Table 91 through Table 97.

11/05/07

3.6

Removed note 1 from Table 52, page 28. FMAX of clock is not an applicable limitation.

Revised DDR2 memory interface performance in Table53, page29.

Revised Table 55 to add ISE 9.2i SP3 where applicable.

Removed XC5VSX95T -3 speed grade support from applicable tables.

Removed unsupported I/O standard (LVPECL_33) from Table 58 and added LVPECL_25.

Added TSMCO and TSMCKBY to Table 70, page 51.

Revised note 3 in Table 76, page 57 and Table77, page58.

Clarified notes in Table 87 to Table 90, and Table 94 to Table 97.

Revised note 1 in Table 99.

12/11/07

3.7

Added new devices (XC5VLX20T, XC5VLX155, and XC5VLX155T) throughout document.

Removed -3 speed grade from XC5VSX95T device lists.

Added Table 31, page 16.

Revised Virtex-5 Device Pin-to-Pin Output Parameter Guidelines in Table 87 through Table 90, and

Virtex-5 Device Pin-to-Pin Input Parameter Guidelines in Table 90 and Table 92 through Table 97. Also

revised Note 1 on Table 92 through Table 97.

Revised Note 1 on Table 99.

02/05/08

3.8

Updated date on version 3.7. Other minor typographical edits.

Updated the sentence: Xilinx does not specify the current or I/O behavior for other power-on sequences,

on page 6.

Added values and notes to Table 27, page 14. Removed ICCINTQ since it is included in Table 4, page 3.

Combined IVTTRXCQ into IVTTRXQ values.

Revised TLLSKEW values in Table 34, page 17.

Revised RXPPMTOL values and note 1 in Table 35, page 18.

Revised -2 performance value for SPI-4.2 in Table 53, page 29.

Added TIODDO_T, TIODDO_IDATAIN, TIODDO_ODATAIN, and Note 3 to Table 64, page 44.

Split out the FMAX rows in Table 71 and the FOUTMAX rows in Table 74, revised -2 value for smallest

devices in both tables.

Added Table 75: PLL in PMCD Mode Switching Characteristics, page 56.

Updated Table 4 and Table 84 to Table 98 to match speed grade designations listed in Table 54.

Revised Note 1 on Table 96 and Table 97.

Date

Version

Revision

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