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參數(shù)資料
| 型號： | HV57908DG |
| 廠商： | SUPERTEX INC |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | 8 MHz, 64-Channel Serial To Parallel Converter With Push-Pull Outputs |
| 中文描述： | EL DISPLAY DRIVER, CQFP80 |
| 封裝： | CERAMIC, QFP-80 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大小： | 459K |
| 代理商： | HV57908DG |
2
HV57908
Symbol
Parameter
Min
Max
Units
V
DD
V
PP
V
IH
V
IL
f
CLK
T
A
Logic supply voltage
4.5
5.5
V
Output voltage
8
80
V
High-level input voltage
V
DD
-0.5
0
V
Low-level input voltage
0.5
V
Clock frequency
8
MHz
Operating free-air temperature
Plastic
-40
+85
°
C
Ceramic
-55
+125
Note:
Power-up sequence should be the following:
1.
Connect ground.
2.
Apply V
DD
.
3.
Set all inputs (Data, CLK, Enable, etc.) to a known state.
4.
Apply V
PP
.
5.
The V
PP
should not drop below V
DD
or float during operation.
Power-down sequence should be the reverse of the above.
Electrical Characteristics
(over recommended operating conditions unless noted, T
A
=-40
°
C to +85
°
C)
DC Characteristics
Symbol
I
DD
Parameter
V
DD
supply current
Min
Max
15
Units
mA
Conditions
V
DD
= V
DD
max
f
CLK
= 8MHz
I
PP
High voltage supply current
100
μ
A
Outputs high
100
μ
A
Outputs low
I
DDQ
V
OH
Quiescent V
DD
supply current
High-level output
100
μ
A
All V
IN
= V
DD
I
O
= -15mA, V
PP
= 80V
I
O
= -100
μ
A
I
O
= 12mA, V
PP
= 80V
I
O
= 100
μ
A
V
IH
= V
DD
V
IL
= 0V
I
OC
= 1mA
HV
OUT
Data out
65
V
V
DD
- 0.5
V
V
OL
Low-level output
HV
OUT
Data out
7
V
0.5
V
I
IH
I
IL
V
OC
High-level logic input current
1
μ
A
Low-level logic input current
-1
μ
A
High voltage clamp diode
1
V
Recommended Operating Conditions
AC Characteristics
(T
A
= 85
°
C max. Logic signal inputs and Data inputs have t
r
, t
f
≤
5ns [10% and 90% points])
Symbol
Parameter
Min
Max
Units
Conditions
f
CLK
t
WL
,t
WH
t
SU
t
H
t
ON
, t
OFF
t
DHL
t
DLH
t
DLE
*
t
WLE
t
SLE
*
t
DLE
is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR output to stabilize).
Clock frequency
8
MHz
Clock width high or low
62
ns
Data set-up time before clock rises
10
ns
Data hold time after clock rises
15
ns
Time from latch enable to HV
OUT
Delay time clock to data high to low
500
ns
C
L
= 15pF
C
L
= 15pF
C
L
= 15pF
70
ns
Delay time clock to data low to high
70
ns
Delay time clock to LE low to high
25
ns
Width of LE pulse
25
ns
LE set-up time before clock rises
0
ns
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