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參數(shù)資料
| 型號： | HV5530X |
| 廠商： | SUPERTEX INC |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | 32-Channel Serial To Parallel Converter With Open Drain Outputs |
| 中文描述： | EL DISPLAY DRIVER, UUC40 |
| 封裝： | DIE-45 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 462K |
| 代理商： | HV5530X |
2
Electrical Characteristics
(over recommended operating conditions unless noted)
DC Characteristics
Symbol
Parameter
Min
Max
Units
Conditions
I
DD
V
DD
supply current
15
mA
f
CLK
= 8MHz
F
DATA
= 4MHz
V
IN
= 0V
All outputs high
All SWS parallel
I
DDQ
I
O(OFF)
Quiescent V
DD
supply current
Off state output current
100
μ
A
10
μ
A
I
IH
I
IL
V
OH
High-level logic input current
1
μ
A
V
IH
= V
DD
V
IL
= 0V
I
Dout
= -100
μ
A
I
HVout
= +100mA
I
Dout
= +100
μ
A
I
OL
= -100mA
Low-level logic input current
-1
μ
A
High-level output data out
V
DD
- 1.0V
V
HV
OUT
Data out
15.0
V
1.0
V
V
OC
HV
OUT
clamp voltage
-1.5
V
V
OL
Low-level output voltage
AC Characteristics
(V
DD
= 12V, T
C
= 25
°
C)
Symbol
Parameter
Min
Max
Units
Conditions
f
CLK
t
W
t
SU
t
H
t
ON
t
DHL
t
DLH
t
DLE
t
WLE
t
SLE
Clock frequency
8
MHz
Clock width high or low
62
ns
Data set-up time before clock falls
25
ns
Data hold time after clock falls
10
ns
Turn on time, HV
OUT
from enable
Delay time clock to data high to low
500
ns
R
L
= 2K
to V
PP
MAX
C
L
= 15pF
C
L
= 15pF
100
ns
Delay time clock to data low to high
100
ns
Delay time clock to LE low to high
50
ns
Width of LE pulse
50
ns
LE set-up time before clock falls
50
ns
Recommended Operating Conditions
Symbol
Parameter
Min
Max
Units
V
DD
HV
OUT
Logic supply voltage
10.8
13.2
V
HV5530 and HV5630
-0.3
+300
V
HV5522 and HV5622
-0.3
+220
V
V
IH
V
IL
f
CLK
T
A
High-level input voltage
V
DD
- 2V
V
DD
2.0
V
Low-level input voltage
0
V
Clock frequency
8
MHz
Plastic
-40
+85
°
C
Ceramic
-55
+125
°
C
Note:
Power-up sequence should be the following:
1. Connect ground.
2. Apply V
DD
.
3. Set all inputs to a known state.
Power-down sequence should be the reverse of the above.
High voltage output
Operating free-air temperature
HV5522/HV5530/HV5622/HV5630
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