11-209
Introduction
Although the HV400 was designed as an interface between
a pulse transformer and a power MOSFET, there are
applications for high current MOSFET gate drive controlled
by standard logic. This application note provides a method of
interfacing the HV400 to logic signals. It also reviews the
input control requirements of the HV400. The data sheet for
the HV400 may be found in the “Intelligent Power IC’s” data
book DB304.
HV400 Circuit Schematic
The HV400 schematic is shown in Figure 1. There are
separate outputs for sinking and sourcing current. When the
input goes low, resistor R3 provides base drive for Q2. An
SCR is used to sink large currents. Transistor Q2 triggers
SCR1 at both the anode and cathode gates. This triggering
sequence begins as soon as D4 becomes reverse biased;
the triggering delay time is then independent of the input fall
time. Resistor R4 provides a base discharge path for Q1.
Diode D6 increases the input hysteresis to reduce the
chances that ringing at the input or output will trigger the
SCR. Resistors R1 and R2 remove excess stored charge
from the SCR and also help prevent false triggering. Diode
D5 clamps the input low voltage.
A high input turns on Q1. Diodes D2 and D3, along with D1,
prevent Q1 from saturating. Diode D1 also provides a means
of passing charge from the input to the supply.
HV400 Input Characteristics
The HV400 is a non inverting current buffer. Pin 2 is the input
control pin. For the output to be high, the input must also be
high. This requires at least 12mA since R3 is approximately
1250
. Additional input current is required for the base
current of Q1. The input driver should be capable of sourcing
200mA for a few hundred nanoseconds to achieve a 3A
output current pulse but much less is required for smaller
output currents due to the change in transistor gain with
current and voltage. The input voltage should be 2V higher
than the desired output voltage.
To set the output into the low state, the input voltage must
drop 1V below the output. This can be accomplished by
terminating the pin 2 input current since R3 acts as a pull-
down resistor. The input voltage should be no more than 2V
above pins 4 and 5 to make sure that Q1 will not turn back
on.
FIGURE 1. MOSFET DRIVER SCHEMATIC
Once the output is triggered low, it will remain low until the
current into the output, pins 3 and 6, drops below 10mA and
the SCR unlatches. The input must not go positive until the
SCR unlatches and has had time to recover its voltage
blocking capability defined by the “minimum off time” specifi-
cation.
Logic Level Input
There are many instances where the control signal is a logic
level referenced to the source of the MOSFET, i.e. logic
ground and the source are at nearly the same potential. For
example, forward, flyback and push-pull switch mode power
supplies use power MOSFET’s with grounded sources.
The Intersil ICL7667 is a dual MOSFET driver that converts
TTL/CMOS level signals into the higher voltages required for
gate drives. The combination HV400 and ICL7667 results in
a low cost, high output current, logic level input MOSFET
driver. The circuit schematic is shown in Figure 2. One of the
ICL7667 outputs becomes the input for the HV400 and the
other is connected in parallel with the HV400 output. Since
the ICL7667 is a CMOS product, its outputs swing rail-to-rail.
Based on the HV400 input requirements, it should be
apparent that a low impedance, high voltage (i.e. 15V)
CMOS output is ideal for driving the HV400 input.
PIN 7
POWER INPUT
PIN 2
D3
D2
D1
R4
R2
Q1
PIN 8
SOURCE OUTPUT
PINS 3 AND 6
SINK OUTPUT
PIN 1
SUPPLY
CONTROL INPUT
D4
D6
Q2
R3
D5
R1
PINS 4 AND 5
RETURN
HIGH CURRENT LOGIC LEVEL MOSFET DRIVER
Author: John Prentice
No. AN9301
April 1994
Application Note
Copyright
Intersil Corporation 1993