參數(shù)資料
型號(hào): HT95L300
廠商: Holtek Semiconductor Inc.
英文描述: 8-Bit LCD Type Phone Controller MCU
中文描述: 8位LCD型電話MCU控制器
文件頁(yè)數(shù): 14/42頁(yè)
文件大?。?/td> 768K
代理商: HT95L300
HT95L100/10P
Rev. 0.10
14
October 1, 2002
Preliminary
Once a Sleep mode or Idle mode wake-up event occurs,
it will take SST delay time (1024 system clock period) to
resume to Green mode. In other words, a dummy period
is inserted after a wake-up. If the wake-up results from
an interrupt acknowledge signal, the actual interrupt
subroutine execution will be delayed by one or more cy-
cles. If the wake-up results in the next instruction execu-
tion, this will be executed immediately after the dummy
period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the Sleep mode
or Idle mode.
The Sleep mode or Idle mode is initialized by the HALT
instruction and results in the following.
The system clock will be turned off.
The WDT function will be disabled if the WDT clock
source is the instruction clock.
The WDT function will be disabled if the WDT clock
source is the 32768Hz in Idle mode.
The WDT will still function if the WDT clock source is
the WDT OSC.
If the WDT function is still enabled, the WDT counter
and WDT prescaler will be cleared and recounted
again.
The contents of the on chip RAM and registers remain
unchanged.
All the I/O ports maintain their original status.
The flag PD is set and the flag TO is cleared by hard-
ware.
Reset
There are three ways in which a reset can occur.
Power on reset.
A low pulse onto RES pin.
WDT time-out.
After these reset conditions, the Program Counter and
Stack Pointer will be cleared to 0.
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem is reset or awakes from the Sleep or Idle operation
mode.
By examining the processor status flags PD and TO, the
software program can distinguish between the different
chip resets .
TO
PD
Reset Condition
0
0
Power on reset
u
u
External reset during Normal mode or
Green mode
0
1
External reset during Sleep mode or
Idle mode
1
u
WDT time-out during Normal mode or
Green mode
1
1
WDT time-out during Sleep mode or
Idle mode
Note: u means unchanged
The functional units chip reset status are shown below:
Program Counter
000H
Interrupt
Disabled
Prescaler
Cleared
WDT
Cleared
After a master reset, WDT
begins counting.
(If WDT function is enabled
by mask option)
Timer/EventCounter0/1 Off
Input/output Port
Input mode
Stack Pointer
Pointstothetopofthestack
;
7
% % 5
% =
8
Reset circuit
3
"
3
4 "
1
C
*
% A
"
4
3
"
7 >
4 " " "
7
"
Reset configuration
7
;
"
" "
Reset timing chart
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