參數(shù)資料
型號(hào)： HT95A400
廠商： Holtek Semiconductor Inc.
英文描述： Time-Delay Relay; Mounting Type:Plug In; Relay Mounting:Plug-In
中文描述： I / O型電話8位微控制器
文件頁數(shù)： 13/48頁
文件大?。?/td> 360K
代理商： HT95A400
HT95AXXX
Rev. 1.20
13
May 26, 2004
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority
Vector
External interrupt
1
04H
Timer/Event Counter 0 interrupt
2
08H
Timer/Event Counter 1 interrupt
3
0CH
Real time clock interrupt
4
14H
Dialer I/O interrupt
5
18H
Priority of the Interrupt
EMI, EEI, ET0I, ET1I, ERTCI and EDRI are used to con-
trol the enabling/disabling of interrupts. These bits pre-
vent the requested interrupt from being serviced. Once
the interrupt request flags (EIF, T0F, T1F, RTCF, DRF)
are set by hardware or software, they will remain in the
INTC0 or INTC1 registers until the interrupts are ser-
viced or cleared by a software instruction.
It is recommended that a program should not use the
CALL subroutine within the interrupt subroutine. Inter-
rupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
one stack is left and enabling the interrupt is not well
controlled, the original control sequence will be dam-
aged once the CALL operates in the interrupt subrou-
tine.
Oscillator Configuration
There are two oscillator circuits in the controller, the ex-
ternal 32768Hz crystal oscillator and internal WDT
OSC.
The 32768Hz crystal oscillator and frequency-up con-
version circuit (32768Hz to 3.58MHz) are designed for
dual system clock source. It is necessary for frequency
conversion circuit to add external RC components to
make up the low pass filter that stabilize the output fre-
quency 3.58MHz (see the oscillator circuit).
The WDT OSC is a free running on-chip RC oscillator,
and no external components are required. Even if the
system enters the Idle mode (the system clock is
stopped), the WDT OSC still works within a period of
78 s normally. When the WDT is disabled or the WDT
source is not this RC oscillator, the WDT OSC will be
disabled.
Watchdog Timer
WDT
The WDT clock source is implemented by a WDT OSC
or external 32768Hz or an instruction clock (system
clock divided by 4), determined by the mask option. This
timer is designed to prevent a software malfunction or
sequence from jumping to an unknown location with un-
predictable results. The Watchdog Timer can be dis-
abledbymaskoption.IftheWatchdogTimerisdisabled,
all the executions related to the WDT result in no opera-
tion.
If the device operates in a noisy environment, using the
on-chip WDT OSC or 32768Hz crystal oscillator is
strongly recommended.
When the WDTclock source is selected, it will be first di-
vided by 512 (9-stage) to get the nominal time-out pe-
riod. By invoking the WDT prescaler, longer time-out
periods can be realized. Writing data to WS2, WS1,
WS0 can give different time-out periods.
'
0
1 2 3
$ B
'
/
'
0
* B
'
,
'
/
'
/
5 /
%
1
0
/
'
) % * + , - .
Watchdog Timer
%
8 1
)
4
8
4
System Oscillator Circuit
Register
Label
Bits
R/W
Function
WDTS
(09H)
WS0
WS1
WS2
0
1
2
RW
Watchdog Timer division ratio selection bits
Bit 2, 1, 0=000, Division ratio=1:1
Bit 2, 1, 0=001, Division ratio=1:2
Bit 2, 1, 0=010, Division ratio=1:4
Bit 2, 1, 0=011, Division ratio=1:8
Bit 2, 1, 0=100, Division ratio=1:16
Bit 2, 1, 0=101, Division ratio=1:32
Bit 2, 1, 0=110, Division ratio=1:64
Bit 2, 1, 0=111, Division ratio=1:128
7~3
RW
Unused bit. These bits are read/write-able.
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