HT95L100/10P
Rev. 0.10
12
October 1, 2002
Preliminary
Oscillator configuration
There are two oscillator circuits in the controller, the ex-
ternal 32768Hz crystal oscillator and internal WDT
OSC.
The 32768Hz crystal oscillator and frequency-up con-
version circuit (32768Hz to 3.58MHz) are designed for
dual system clock source. It is necessary for frequency
conversion circuit to add external RC components to
make up the low pass filter that stabilize the output fre-
quency 3.58MHz (see the oscillator circuit).
The WDT OSC is a free running on-chip RC oscillator,
and no external components are required. Even if the
system enters the Idle mode (the system clock is
stopped), the WDT OSC still works within a period of
78 s normally. When the WDT is disabled or the WDT
source is not this RC oscillator, the WDT OSC will be
disabled.
Watchdog Timer
WDT
The WDT clock source is implemented by a WDT OSC
or external 32768Hz or an instruction clock (system
clock divided by 4), determined by the mask option. This
timer is designed to prevent a software malfunction or
sequence from jumping to an unknown location with un-
predictable results. The Watchdog Timer can be dis-
abledbymaskoption.IftheWatchdogTimerisdisabled,
all the executions related to the WDT result in no opera-
tion.
If the device operates in a noisy environment, using the
on-chip WDT OSC or 32768Hz crystal oscillator is
strongly recommended.
When the WDT clock source is selected, it will be first di-
vided by 512 (9-stage) to get the nominal time-out
period. By invoking the WDT prescaler, longer time-out
periods can be realized. Writing data to WS2, WS1,
WS0 can give different time-out periods.
The WDT OSC period is 78 s. This time-out period may
vary with temperature, VDD and process variations. The
WDT OSC always works for any operation mode.
If the instruction clock is selected as the WDT clock
source, the WDT operates in the same manner except
in the Sleep mode or Idle mode. In these two modes, the
WDT stops counting and lose its protecting purpose. In
this situation the logic can only be re-started by external
logic.
If the WDT clock source is the 32768Hz, the WDT also
operates in the same manner except in the Idle mode.
When in the Idle mode, the 32768Hz stops, the WDT
stops counting and lose its protecting purpose. In this
situation the logic can only be re-started by external
logic.
The high nibble and bit3 of the WDTS are reserved for
user defined flags, which can be used to indicate some
specified status.
The WDT time-out under Normal mode or Green mode
will initialize chip reset and set the status bit TO . But
in the Sleep mode or Idle mode, the time-out will initial-
ize a warm reset and only the program counter and
stack pointer are reset to 0. To clear the WDT contents
(including the WDT prescaler), three methods are
adopted; external reset (a low level to RES pin), soft-
ware instruction and a HALT instruction.
The software instruction include CLR WDT and the
other set CLR WDT1 and CLR WDT2 . Of these two
types of instruction, only one can be active depending
on the mask option WDT instr . If the CLR WDT is se-
lected (i.e. One clear instruction), any execution of the
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System oscillator circuit
Register
Label
Bits
R/W
Function
WDTS
(09H)
WS0
WS1
WS2
0
1
2
RW
Watchdog Timer division ratio selection bits
Bit 2, 1, 0=000, Division ratio=1:1
Bit 2, 1, 0=001, Division ratio=1:2
Bit 2, 1, 0=010, Division ratio=1:4
Bit 2, 1, 0=011, Division ratio=1:8
Bit 2, 1, 0=100, Division ratio=1:16
Bit 2, 1, 0=101, Division ratio=1:32
Bit 2, 1, 0=110, Division ratio=1:64
Bit 2, 1, 0=111, Division ratio=1:128
7~3
RW
Unused bit. These bits are read/write-able.