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參數(shù)資料
| 型號： | HT9032 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | Calling Line Identification Receiver |
| 中文描述： | 來電線路識別接收器 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 222K |
| 代理商： | HT9032 |
HT9032
7
April 6, 2000
Functional Description
The HT9032 is designed to be the physical layer
demodulator for products targeted for the caller
ID market. The data signaling interface should
conform to Bell 202, which is described as fol-
lows:
Analog, phase coherent, frequency shift keying
Logical 1 (Mark)=1200+/ 12Hz
Logical 0 (Space)=2200+/ 22Hz
Transmission rate=1200bps
Data application=serial, binary,
asynchronous
The interface should be arranged to allow sim-
ple data transmission from the terminating
central office, to the CPE (Customer Premises
Equipment), only when the CPE is in an
on-hook state. The data will be transmitted in
the silent period between the first and second
power ring before a voice path is established.
The transmission level from the terminating
C.O.willbe 13.5dBm+/ 1.0.Theworstcaseat-
tenuation through the loop is expected to be
20dB. The receiver therefore, should have a
sensitivity of approximately 34.5dBm to han-
dle the worst case installations. The ITU-T V.23
is also using the FSK signaling scheme to
transmit data in the general switched tele-
phone network. For mode 2 of the V.23, the
modulation rate and characteristic frequencies
are listed below:
Analog, phase coherent, frequency shift keying
Logical 1 (Mark)=1300Hz
Logical 0 (Space)=2100Hz
Transmission rate=1200bps
Since the band pass filter of the HT9032 can
pass the V.23 signal, hence the HT9032 also can
demodulate the V.23 signal.
Ring detection
The data will be transmitted in the silent pe-
riodbetweenthefirstandsecondpowerringbe-
fore a voice path is established. The HT9032
should first detect a valid ring and then per-
form the FSK demodulation. The typical ring
detection circuit of the HT9032 is depicted be-
low. The power ring signal is first rectified
through a bridge circuit and then sent to a re-
sistor network that attenuates the incoming
power ring. The values of resistors and capaci-
tor given in the figure have been chosen to pro-
vide a sufficient voltage at RDET1 pin to turn
on the Schmitt Trigger input with approxi-
mately a 40 Vrms or greater power ring input
from tip and ring. When V
T+
of the Schmitt is
exceeded, the NMOS on the pin RTIME will be
driven to saturation discharging capacitor on
RTIME. This will initialize a partial power up,
with only the portions of the part involved with
the ring signal analysis enabled, including
RDET2pin.WithRDET2pinenabled,aportion
of the power ring above 1.2V is fed to the ring
analysis circuit. Once the ring signal is quali-
fied, the RDET pin will be sent low.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HT9032A(16DIP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| HT9032A(16SOP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| HT9032B | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Calling Line Identification Receiver |
| HT9032B(8DIP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| HT9032B-A | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Calling Line Identification Receiver |
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