參數(shù)資料
型號: HT86070
廠商: Holtek Semiconductor Inc.
英文描述: Voice Synthesizer 8-Bit MCU
中文描述: 語音合成器8位微控制器
文件頁數(shù): 12/40頁
文件大?。?/td> 256K
代理商: HT86070
HT86030/HT86070
Rev. 1.10
12
May 25, 2006
however, may yield different results from those in-
tended. The TO and PDF flags can only be changed by
a Watchdog Timer overflow, chip power-up, or clearing
the Watchdog Timer and executing the HALT instruc-
tion. The Z, OV, AC, and C flags reflect the status of the
latest operations.
On entering the interrupt sequence or executing the
subroutine call, the status register will not be automati-
cally pushed onto the stack. If the contents of the status
is important, and if the subroutine is likely to corrupt the
status register, the programmer should take precautions
and save it properly.
Interrupts
The HT86030/HT86070 provides an external interrupt,
three 16-bit programmable timer interrupts, and an 8-bit
programmable timer interrupt. The Interrupt Control reg-
isters (INTC:0BH, INTCH:1EH) contain the interrupt
control bits to set to enable/disable and the interrupt re-
quest flags.
Once an interrupt subroutine is serviced, all other inter-
rupts will be blocked (by clearing the EMI bit). This
schememaypreventanyfurtherinterruptnesting.Other
interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If a certain in-
terrupt needs servicing within the service routine, the
EMI bit and the corresponding INTC/INTCH bit may be
set to allow interrupt nesting. If the stack is full, the inter-
rupt request will not be acknowledged, even if the re-
lated interrupt is enabled, until the SP is decremented. If
immediate service is desired, the stack must be pre-
vented from becoming full.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack and then
branching to subroutines at the specified location(s) in
the program memory. Only the program counter is
pushed onto the stack. The programmer must save the
contents of the register or status register (STATUS) in
advance if they are altered by an interrupt service pro-
gram which corrupts the desired control sequence.
External interrupt is triggered by a high-to-low/
low-to-high transition of INT pin which sets the related
interrupt request flag (EIF:bit 4 of INTC). When the inter-
rupt is enabled, and the stack is not full and the external
interrupt is active, a subroutine call to location 04H will
occur. The interrupt request flag (EIF) and EMI bits will
be cleared to disable other interrupts.
The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event counter 0 interrupt re-
quest flag (T0F:bit 5 of INTC), caused by a Timer/Event
Counter 0 overflow. When the interrupt is enabled, and
the stack is not full and the T0F bit is set, a subroutine
call to location 08H will occur. The related interrupt re-
quest flag (T0F) will be reset and the EMI bit cleared to
disable further interrupts.
The internal Timer/Event Counter 1 interrupt is initial-
ized by setting the Timer/Event Counter 1 interrupt re-
quest flag (T1F:bit 6 of INTC), caused by a Timer/Event
Counter 1 overflow. When the interrupt is enabled, and
the stack is not full and the T1F bit is set, a subroutine
call to location 0CH will occur. The related interrupt re-
quest flag (T1F) will be reset and the EMI bit cleared to
disable further interrupts.
The internal Timer Counter 3 interrupt is initialized by
setting the Timer Counter 3 interrupt request flag
(T3F:bit 1 of INTCH), caused by a Timer Counter 3 over-
flow. When the interrupt is enabled, and the stack is not
full and the T3F bit is set, a subroutine call to location
14H will occur. The related interrupt request flag (T3F)
will be reset and the EMI bit cleared to disable further in-
terrupts.
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
takeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by system power-up or executing the CLR WDT instruction.
PDF is set by executing the HALT instruction.
5
TO
TO is cleared by system power-up or executing the CLR WDT or HALT instruction.
TO is set by a WDT time-out.
6~7
Unused bit, read as 0
Status (0AH) Register
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