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參數(shù)資料
| 型號： | HT86030_06 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | Voice Synthesizer 8-Bit MCU |
| 中文描述： | 語音合成器8位微控制器 |
| 文件頁數(shù)： | 14/40頁 |
| 文件大小： | 256K |
| 代理商： | HT86030_06 |
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HT86030/HT86070
Rev. 1.10
14
May 25, 2006
Watchdog Timer
WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys-
tem clock divided by 4), decided by mask options. This
timer is designed to prevent a software malfunction or
sequence jumping to an unknown location with unpre-
dictable results. The Watchdog Timer can be disabled
by mask option. If the Watchdog Timer is disabled, all
theexecutionsrelatedtotheWDTresultinnooperation.
Once the internal WDT oscillator (RC oscillator with pe-
riod 78 s normally) is selected, it is first divided by 256
(8-stages) to get the nominal time-out period of approxi-
mately 20 ms. This time-out period may vary with tem-
perature, VDD and process variations. By invoking the
WDT prescaler, longer time-out period can be realized.
Writing data to WS2, WS1, WS0 (bit 2,1,0 of
WDTS(09H)) can give different time-out period.
If WS2, WS1, WS0 all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 2.6 sec-
onds.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
a chip reset and set the status bit TO . Whereas in
the HALT mode, the overflow will initialize a warm re -
set only the Program Counter and SP are reset to zero.
To clear the contents of the WDT (including the WDT
prescaler), three methods are adopted; external reset
(external reset (a low level to RES), software instruc-
tions, or a HALT instruction. The software instruction is
CLR WDT and execution of the CLR WDT instruc-
tion will clear the WDT.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS (09H) Register
Power Down
HALT
The HALT mode is initialized by a HALT instruction and
results in the following:
The system oscillator will be turned off but the WDT os-
cillatorkeepsrunning(iftheWDToscillatorisselected).
The contents of the on chip RAM and registers remain
unchanged.
WDT and WDT prescaler will be cleared and recount
again.
All I/O ports maintain their their original status.
The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDToverflow per-
forms a warm reset . By examining the TO and PDF
flags, the reason for the chip reset can be determined.
The PDF flag is cleared when the system powers-up or
executes the CLR WDT instruction, and is set when
the HALT instructionisexecuted.TheTOflagissetifa
WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and SP. The other maintain
their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by a mask option. Awakening from an I/O port
stimulus, the program will resume execution of the next
instruction. If awakening from an interrupt, two se-
quences may happen. If the related interrupt is disabled
or the interrupt is enabled by the stack is full, the pro-
gram will resume execution at the next instruction. If the
interrupt is enabled and the stack is not full, the regular
interrupt response takes place.
Once a wake-up event occurs, it takes 1024 system
clock period to resume normal operation. In other
words, a dummy cycle period will be inserted after a
wake-up. If the wake-up results from an interrupt ac-
knowledge, the actual interrupt subroutine will be de-
layed by one more cycle. If the wake-up results in next
instruction execution, this will be executed immediately
after a dummy period is finished. If an interrupt request
flag is set to 1 before entering the HALT mode, the
wake-up function of the related interrupt will be dis-
abled. To minimize power consumption, all I/O pins
should be carefully managed before entering the HALT
status.
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Watchdog Timer
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PDF描述 |
|---|---|
| HT86070 | Voice Synthesizer 8-Bit MCU |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HT86070 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Voice Synthesizer 8-Bit MCU |
| HT86072 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Voice Synthesizer 8-Bit MCU |
| HT86072(68PLCC) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| HT86144 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Voice Synthesizer 8-Bit MCU |
| HT86144(68PLCC) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
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