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參數(shù)資料
| 型號： | HT83C51DC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RY Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 09V; Output Voltage (Vdc): 12V; Power: 1W; On/Off Pin; 1kVDC Isolation; UL94V-0 Package Material; Optional Continuous Short Circuit Protected; Internal linear regulator; Efficiency to 70% |
| 中文描述： | 高溫83C51單片機 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 89K |
| 代理商： | HT83C51DC |
4
HT83C51
OSCILLATOR CHARACTERISTICS
IDLE MODE
MEMORY
An instruction that sets the PCON.0-bit causes that to be
the last instruction executed prior to going into Idle
mode. In the Idle mode, the internal clock to the CPU is
gated off but not to the Interrupt, Timer, and Serial Port
functions. The PCA can be programmed to either pause
or continue operating during Idle Mode. The CPU status
is completely preserved and all registers maintain their
previous values during Idle Mode. The port pins hold the
logical values that they had at the time the Idle mode
was activated. ALE and PSENn hold at logic high levels.
Idle mode can be terminated in two ways. Activation of any
enabled interrupt will cause the PCON.0-bit to be cleared
by hardware, terminating Idle mode. The interrupt will be
serviced, and following the RETI instruction execution, the
instruction after the one that caused Idle mode will be
executed. Recovery from Idle mode is 3 oscillator periods
plus 3 instruction cycles.
The HT51 has a separate address space for Program and
Data Memory. Internally the HT51 contains 8 Kbytes of
Program Memory and 256 bytes of Data Memory. It can
address up to 64 Kbytes of external Data Memory and 64
Kbytes of external Program Memory.
There are 8 Kbytes of internal program memory in the
HT51. The EAn pin must be tied to Vdd (power) to enable
access to internal program memory locations. When the
EAn pin is tied to Vdd, program fetches to addresses
0000H to 1FFFH will be made to internal program ROM.
Program fetches to addresses 2000H through FFFFH are
to external memory. The EAn pin must be tied to Vss
(ground) to enable access to external program memory
locations 0000H through 1FFFH.
The HT51 implements 256 bytes of internal data RAM. The
upper 128 bytes of this RAM occupy a parallel address
space to the Special Function Registers (SFRs). The CPU
determines if the internal access to an address above 7FH
is to the upper 128 bytes of RAM or to the SFR space by the
addressing mode of the instruction. If direct addressing is
used, the access is to the SFR space. If indirect addressing
is used, the access is to the internal RAM. Stack operations
are indirectly addressed so the upper portion of RAM can
be used as stack space.
The HT51 contains three 16-bit timer/counters. Each of
these are made up of two 8-bit registers (THx, TLx where
x = 0, 1, or 2). Each of these three can operate in either
timer or counter mode. In the timer mode, the TLx register
is incremented once every machine cycle (12 oscillator
periods). The count rate is 1/12th of the oscillator frequency.
In counter mode, the register is incremented when a 1 to 0
transition is detected on the alternate function input
corresponding to that timer (Tx where x = 0, 1, or 2). The
maximum rate of count in counter mode that the HT51 can
detect is 1/24th of the oscillator frequency.
The input is XTAL1 and the output is XTAL2 for an inverting
amplifier which can be used as an on-chip oscillator as
shown in Figure 1. Make sure to qualify the crystal or
alternate timing source over the temperature range of the
intended application. If an external clock source such as
the HTOSC is used, XTAL1 should be driven while XTAL2
floats as shown in Figure 2. There are no duty cycle
requirements on the external clock signal, but minimum
and maximum high and low times must be observed.
For C1 and C2 values,
contact crystal manufacturer
Figure 1. Oscillator Connections
XTAL 2
XTAL 1
Vss
N/C
External
Oscillator
Signal
Figure 2. External Clock Drive Configuration
The other way that Idle mode can be terminated is through
a hardware reset, which can be accomplished by holding
the RST pin high for 4 clock periods while the clock is
running. Exiting Idle mode with a hardware reset will retain
the contents of the on-chip RAM but the values in the SFRs
will be lost and program execution will begin at address 0.
C2
C1
XTAL 2
XTAL 1
Vss
TIMER/COUNTERS
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