參數(shù)資料
型號: HT83C51DB
廠商: Electronic Theatre Controls, Inc.
英文描述: HIGH TEMPERATURE 83C51 MICROCONTROLLER
中文描述: 高溫83C51單片機
文件頁數(shù): 3/12頁
文件大?。?/td> 89K
代理商: HT83C51DB
3
HT83C51
PIN DESCRIPTIONS
VDD: +5V Supply Voltage
VSS: Circuit Ground
Port 0 (P0.0 - P0.7): Port 0 is an 8-bit bidirectional I/O port.
If external Program and/or Data memory are used, port 0
cannot be used for general purpose I/O. During accesses
to external Program and Data memory Port 0 is used as the
low-order multiplexed address and data bus. In this mode,
Port 0 pins use strong internal pullups when emitting 1’s,
and are TTL compatible. If external Program and Data
memory are not used, Port 0 pins can be used as general
purpose I/O. When the Port pins have 1’s written to them
in I/O mode, the pins are floating and can be driven as
inputs. An external pullup is required to generate logic high
output in I/O mode.
Port 1 (P1.0 - P1.7): Port 1 is an 8-bit bidirectional I/O port
with internal pullups. The output buffers can drive TTL
loads. When the Port 1 pins have 1’s written to them, they
are pulled high by the internal pullups and can be used as
inputs in this state. As inputs, any pins that are externally
pulled low will source current because of the pullups. In
addition, Port 1 pins have the alternate uses shown in the
table below:
Port 2 (P2.0 - P2.7): Port 2 is an 8-bit bidirectional I/O port
with internal pullups. The output buffers can drive TTL
loads. When the Port 2 pins have 1’s written to them, they
are pulled high by the internal pullups and can be used as
inputs in this state. As inputs, any pins that are externally
pulled low will source current because of the pullups.
Port 2 is used as the high-order address byte during
accesses to external Program Memory and during accesses
to external Data Memory that use 16-bit addresses (i.e.
MOVX @DPTR). It uses strong internal pullups when
emitting 1’s in this mode. During accesses to external Data
Memory that use 8 bit addresses, Port 2 emits the contents
of the P2 SFR.
Port 3 (P3.0 - P3.7): Port 3 is an 8-bit bidirectional I/O port
with internal pullups. The output buffers can drive TTL
Port
Pin
Name
Alternate Function
P1.0
T2
External clock input to timer/ Clock out
P1.1
T2EX
Timer/Counter 2 Capture/Reload trigger and
direction control
P1.2
ECI
External count input to PCA
P1.3
CEX0
External I/O for PCA capture/compare Module 0
P1.4
CEX1
External I/O for PCA capture/compare Module 1
P1.5
CEX2
External I/O for PCA capture/compare Module 2
P1.6
CEX3
External I/O for PCA capture/compare Module 3
P1.7
CEX4
External I/O for PCA capture/compare Module 4
loads. When the Port 3 pins have 1’s written to them, they
are pulled high by the internal pullups and can be used as
inputs in this state. As inputs, any pins that are externally
pulled low will source current because of the pullups. In
addition, Port 3 pins have the alternate uses shown in the
table below:
Port Pin
Alternate Name Alternate Function
P3.0
RXD
Serial port input
P3.1
TXD
Serial port output
P3.2
INT0n
External interrupt 0
P3.3
INT1n
External interrupt 1
P3.4
T0
External clock input for Timer 0
P3.5
T1
External clock input for Timer 1
P3.6
WRn
External Data Memory write strobe
P3.7
RDn
External Data Memory read strobe
RST: Reset input. A high on this input for 2 or more
oscillator periods while the oscillator is running resets the
device. All ports and Special Function Registers will be
reset to their default conditions. Internal data memory is
undefined after reset. Program execution will begin within
12 oscillator periods (one machine cycle) after the RST
signal is brought low. RST contains an internal pulldown
resistor to allow implementing power-up reset with only an
external capacitor.
ALE: Address Latch Enable. The ALE output is a pulse for
latching the low byte of the address during accesses to
external memory. In normal operation the ALE pulse is
output every 6th oscillator cycle and may be used for
external timing or clocking. However, during each access
to external Data Memory (MOVX instruction), one ALE
pulse is skipped. If desired, ALE operation can be disabled
by setting bit 0 of SFR 8EH. When this bit is set, ALE is
active only during a MOVX instruction. Otherwise, the pin
is held low. When ALE is disabled, program execution
must be limited to the internal 8K program ROM.
PSENn: Program Store Enable. This active low signal is
the read strobe to the external program memory. PSENn
is activated every 6th oscillator cycle except that 2 PSENn
activations are skipped during external data memory
accesses.
EAn: External Access Enable. The EAn pin must be
strapped to VSS for the HT51 to fetch code from external
Program Memory locations 0000H to 1FFFH. The EAn pin
must be strapped to VDD for internal program execution
from memory locations 0000H to 1FFFH.
XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.
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