參數(shù)資料
型號(hào)： HT82K94A
廠商： Holtek Semiconductor Inc.
英文描述： USB Multimedia Keyboard Encoder 8-Bit MCU
中文描述： 的USB多媒體鍵盤編碼器8位微控制器
文件頁數(shù)： 12/44頁
文件大小： 295K
代理商： HT82K94A
HT82K94E/HT82K94A
Rev. 1.00
12
November 22, 2005
If the device operates in a noisy environment, using the
on-chip 32kHz RC oscillator (WDT OSC) is strongly rec-
ommended, since the HALT will stop the system clock.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS (09H) Register
The WDT overflow under normal operation will initialize
a chip reset and set the status bit TO . But in the
HALT mode, the overflow will initialize a warm reset
and only the Program Counter and SP are reset to zero.
To clear the contents of the WDT (including the WDT
prescaler), three methods are employed; external reset
(a low level to RES), software instruction and a HALT
instruction. The software instruction include
CLR
WDT
and the other set
CLR WDT1
and
CLR
WDT2 . Of these two types of instruction, only one can
be active depending on the ROM code option
CLR
WDT times selection option . If the CLR WDT is se-
lected (i.e. CLRWDT times equal one), any execution of
the CLR WDT instruction will clear the WDT. In the
case wherein CLR WDT1 and CLR WDT2 are cho-
sen (i.e. CLRWDT times is equal to two), these two in-
structions must be executed to clear the WDT,
otherwise, the WDT may reset the chip as a result of
time-out.
Power Down Operation
HALT
The HALT mode is initialized by the HALT instruction
and results in the following:
The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
The contents of the on-chip RAM and registers remain
unchanged.
WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
All of the I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt except external interrupt
PA4/EXT, an external falling edge signal on I/O ports or
a WDT overflow. An external reset causes a device ini-
tialization and the WDT overflow performs a warm re-
set . After the TO and PDF flags are examined, the
cause for chip reset can be determined. The PDF flag is
cleared by a system power-up or executing the CLR
WDT instruction and is set when executing the HALT
instruction. The TO flag is set if the WDT time-out oc-
curs, and causes a wake-up that only resets the Pro-
gram Counter and SP, the others remain in their original
status.
The I/O ports wake-up and interrupt methods can be
considered as a continuation of normal execution. Each
bit in the Port A can be independently selected to
wake-up the device by option. PB, PC and PD can also
be selected to wake-up the device by option. Upon
awakening from an I/O port stimulus, the program will
resume execution of the next instruction. If it awakens
fromaninterrupt,twosequencemayoccur.Iftherelated
interrupt is disabled or the interrupt is enabled but the
stack is full, the program will resume execution at the
next instruction. If the interrupt is enabled and the stack
is not full, the regular interrupt response takes place. If
an interrupt request flag is set to 1 before entering the
HALT mode, the wake-up function of the related inter-
rupt will be disabled. Once a wake-up event occurs, it
takes 1024 t
SYS
(system clock period) to resume normal
operation. In other words, a dummy period will be in-
serted after a wake-up. If the wake-up results from an in-
terrupt acknowledge signal, the actual interrupt
subroutine execution will be delayed by one or more cy-
cles. If the wake-up results in the next instruction execu-
tion, this will be executed immediately after the dummy
period is completed.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
Therearethreewaysinwhicharesetcanoccur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set that resets only the Program Counter and SP, leav-
ing the other circuits in their original state. Some regis-
ters remain unchanged during other reset conditions.
Most registers are reset to the initial condition when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
chip resets .
TO PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: u stands for unchanged
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HT82K95E 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:USB Multimedia Keyboard Encoder 8-Bit MCU
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