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參數(shù)資料
| 型號： | HT82K68A-L |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | Multimedia Keyboard Encoder 8-Bit MCU |
| 中文描述： | 多媒體鍵盤編碼器8位微控制器 |
| 文件頁數(shù)： | 11/39頁 |
| 文件大?。?/td> | 269K |
| 代理商： | HT82K68A-L |
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HT82K68E-L/HT82K68A-L
Rev. 1.00
11
August 9, 2007
If the WDToscillator is disabled, the WDTclock may still
come from the instruction clock and operate in the same
manner except that in the HALTstate the WDTmay stop
countingandloseitsprotectingpurpose.Inthissituation
the WDT logic can be restarted by external logic. The
high nibble and bit 3 of the WDTS are reserved for user
definedflags,whichcanbeusedtoindicatesomespeci-
fied status.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS (09H) Register
The WDT overflow under normal operation will initialize
chip reset and set the status bit TO. An overflow in the
HALT mode, initializes a warmreset only when the pro-
gram counter and stack pointer are reset to zero. To
clear the contents of the WDT (including the WDT
prescaler ), three methods are adopted; external reset
(alowleveltoRESET),software instruction(s), or a HALT
instruction. There are two types of software instructions;
CLR WDT and CLR WDT1/CLR WDT2. Of these two
types of instruction, only one can be active depending
on the mask option
CLR WDTtimes selection option .
If the CLR WDT is selected (ie. CLR WDT times equal
one), any execution of the CLR WDT instruction will
clear the WDT. In case CLR WDT1 and CLR WDT2
are chosen (ie. CLRWDTtimes equal two), these two in-
structions must be executed to clear the WDT; otherwise,
the WDT may reset the chip because of the time-out.
Power Down Operation
HALT
The HALT mode is initialized by the HALT instruction
and results in the following...
ThesystemoscillatorwillturnoffbuttheWDToscillator
keeps running (if the WDT oscillator is selected).
The contents of the on–chip RAM and registers
remain unchanged.
WDT and WDT prescaler will be cleared and recount
again (if the WDT clock has come from the WDT
oscillator).
All I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, interrupt, and external falling edge signal
on port A and port C [0:3] or a WDT overflow. An exter-
nal reset causes a device initialization and the WDT
overflow performs a warm reset . Examining the TO
and PDF flags, the reason for chip reset can be deter-
mined. The PDF flag is cleared when system power-up
or executing the CLR WDT instruction and is set when
theHALTinstructionisexecuted.TheTOflagissetifthe
WDT time-out occurs, and causes a wake-up that only
resets the program counter and stack pointer, the others
keep their original status.
On the other hand, awakening from an external interrupt
(PC2), two sequences may happen. If the interrupt is
disabled or the interrupt is enabled but the stack is full,
the program will resume execution at the next instruc-
tion. But if the interrupt is enabled and the stack is not
full, the regular interrupt response takes place.
The port Aor port C [0:3] wake-up can be considered as
a continuation of normal execution. Each bit in port A
can be independently selected to wake up the device by
mask option. Awakening from an I/O port stimulus, the
program will resume execution of the next instruction.
Once a wake-up event occurs, and the system clock
comes from a crystal, it takes 1024 t
SYS
(system clock
period) to resume normal operation. In other words, the
device will insert a dummy period after the wake-up. If
the system clock comes from an RC oscillator, it
continues operating immediately. If the wake-up results
in next instruction execution, this will execute
immediately after the dummy period is completed.
To minimize power consumption, all I/O pins should be
carefully managed before entering the HALT status.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HT82K68E-L | Multimedia Keyboard Encoder 8-Bit MCU |
| HT82K68A | 8-Bit High Performance Peripheral Interface IC For Multiple I/O Products and Multimedia Applications(8位高性能外圍接口集成芯片，用于多I/O口及多媒體器件) |
| HT82K68E | 8-Bit High Performance Peripheral Interface IC For Multiple I/O Products and Multimedia Applications(8位高性能外圍接口集成芯片，用于多I/O口及多媒體器件) |
| HT82K68 | Multimedia Keyboard Encoder OTP |
| HT82K94A | USB Multimedia Keyboard Encoder 8-Bit MCU |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HT82K68E | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Multimedia Keyboard Encoder OTP |
| HT82K68E_07 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Multimedia Keyboard Encoder 8-Bit OTP MCU |
| HT82K68E-L | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Multimedia Keyboard Encoder 8-Bit MCU |
| HT82K68E-L_09 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Multimedia Keyboard Encoder 8-Bit MCU |
| HT82K68E-L_11 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Multimedia Keyboard Encoder 8-Bit MCU |
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