HT82A822R
Rev. 1.10
14
June 29, 2007
Bit No.
Label
Function
0~2, 5
Unused bit, read as 0
3
TE
Defines the TMR active edge of the timer/event counter
In Event counter mode (TM1, TM0)=(0, 1):
1=count on falling edge;
0=count on rising edge
In Pulse width measurement mode (TM1, TM0)=(1, 1):
1=start counting on the rising edge, stop on the falling edge;
0=start counting on the falling edge, stop on the rising edge
4
TON
Enable/disable the timer counting (0=disable; 1=enable)
6
7
TM0
TM1
Defines the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMRC (11H) Register
)
) (
'
)
&
%
"
%
&
6 % ,
( ' A
%
&
%
% ,
&
A
# & 8
%
#
/
( 0
6 % ,
( ' A
%
;
) ( <
#
Timer/Event Counter 0/1
Input/Output Ports
There are 24 bidirectional input/output lines in the mi-
cro-controller, labeled from PAto PC, which are mapped
to the data memory of [12H], [14H] or [16H], respec-
tively. All of these I/O ports can be used for input and
output operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2
rising edge of instruction MOV A,[m] (m=12H, 14H or
16H).Foroutputoperation,allthedataislatchedandre-
mains unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC or
PCC) to control the input/output configuration. With this
control register, CMOS output or Schmitt trigger input
with or without pull-high resistor structures can be re-
configured dynamically (i.e. on-the-fly) under software
control. To function as an input, the corresponding latch
of the control register must write 1 . The input source
also depends on the control register. If the control regis-
terbitis 1 theinputwillreadthepadstate.Ifthecontrol
register bit is 0 the contents of the latches will move to
the internal bus. The latter is possible in the
Read-modify-write
CMOS configurations can be selected. These control
registers are mapped to locations 13H, 15H or 17H.
instruction. For output function,
Afterachipreset,theseinput/outputlinesremainathigh
levels or floating state (depending on the pull-high op-
tions). Each bit of these input/output latches can be set
or cleared by SET [m].i and CLR [m].i (m=12H, 14H
or 16H) instructions.
Some instructions first input data and then follow the
output operations. For example,
SET [m].i ,
CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device.
It is recommended that unused or not bonded out I/O
linesshouldbesetasoutputpinsbysoftwareinstruction
to avoid consuming power under input floating state.