HT7627
Rev. 1.00
3
January 18, 2002
The operation will be explained with reference to the following diagrams:
Step1: t
r
is turned ON and current I
L
(=i1) flows, so that energy is charged in L. At this moment, I
L
(=i1) is increased
from I
Lmin
to reach I
Lmax
in proportion to the on-time period (t
on
) of t
r
.
Step2: When t
r
is turned OFF, Schottky diode (SD) is turned ON in order that L maintains I
L
at I
Lmax
, so that current I
L
(=i2) is released.
Step3: I
L
(=i2) is gradually decreased, I
L
reaches I
Lmin
after a time period of t
open
, so that SD is turned OFF. t
r
will be
turned ON in the next cycle.
In the case of PWM control system, the output voltage is maintained constant by controlling the on-time period (t
on
),
with the oscillator frequency (f
OSC
) being maintained constant.
Voltage detector operation
The HT7627 built-in voltage detector is equipped with a high stability voltage reference which is connected to the nega-
tive of a comparator
denoted as Vref in the following figure for NMOS output voltage detector.
When the voltage drop to the positive input of the comparator (i.e. V
B
) is higher than Vref, V
OUT
goes high, and V
B
is ex-
pressed as V
BH
=V
DD
(R
B
+R
C
) / (R
A
+R
B
+R
C
). If V
DD
is decreased so that V
B
falls to a value less than Vref, the com-
parator output inverts from high to low, V
OUT
goes low, V
C
is high, RC is bypassed, and V
B
becomes: V
BL
=V
DD
R
B
/(R
A
+R
B
), which is less than V
BH
. By so doing, the comparator output will remain low to prevent the circuit from oscil-
lating when V
B
Vref.
If V
DD
falls below the minimum operating voltage, the output becomes undefined. When V
DD
goes from low to V
DD
/ (R
A
+R
B
) > Vref, the comparator output and V
OUT
goes high. The detectable voltage is defined as:
R
B
V
DETECT
( )=
R
R
R
R
R
A
B
C
B
C
Vref
The release voltage is defined as:
V
DETECT
(+)=
R
R
R
R
A
B
C
B
Vref
) (
"
)
)
)
)
*
+ " ,