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參數(shù)資料
| 型號： | HT49R50 |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 13/59頁 |
| 文件大?。?/td> | 339K |
| 代理商： | HT49R50 |
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HT49R50
13
October 22, 1999
Arithmetic and logic unit
ALU
This circuit performs 8-bit arithmetic and logic
operations and provides the following func-
tions:
Arithmetic operations (ADD, ADC, SUB,
SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ etc.)
The ALU not only saves the results of a data op-
eration but also changes the status register.
Status register
STATUS
The status register (0AH) is of 8 bits wide and
contains, a carry flag (C), an auxiliary carry flag
(AC), a zero flag (Z), an overflow flag (OV), a
power down flag (PD), and a watchdog time-out
flag (TO). It also records the status information
and controls the operation sequence.
Except the TO and PD flags, bits in the status
register can be altered by instructions similar
to other registers. Data written into the status
register does not alter the TO or PD flags. Oper-
ations related to the status register, however,
may yield different results from those intended.
The TO and PD flags can only be changed by a
watchdog timer overflow, chip power-up, or
clearing the watchdog timer and executing the
"HALT" instruction. The Z, OV, AC, and C flags
reflect the status of the latest operations.
On entering the interrupt sequence or execut-
ing the subroutine call, the status register will
not be automatically pushed onto the stack. If
the contents of the status is important, and if
the subroutine is likely to corrupt the status
register, the programmer should take precau-
tions and save it properly.
Interrupts
The HT49R50 provides two external inter-
rupts, two internal timer/event counter inter-
rupts, an internal time base interrupt, and an
internal real time clock interrupt. The inter-
rupt control register 0 (INTC0;0BH) and inter-
rupt control register 1 (INTC1;1EH) both
contain the interrupt control bits that are used
to set the enable/disable status and interrupt
request flags.
Labels
Bits
Function
C
0
Cissetiftheoperationresultsinacarryduringanadditionoperationorifabor-
row does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
AC
1
ACissetiftheoperationresultsinacarryoutofthelownibblesinadditionorno
borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.
OV
3
OV is set if the operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD
4
PD is cleared by either a system power-up or executing the "CLR WDT" instruc-
tion. PD is set by executing the "HALT" instruction.
TO
5
TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" in-
struction. TO is set by a WDT time-out.
6
Undefined, read as "0"
7
Undefined, read as "0"
Status register
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