
HT49C10
15
September 28, 1999
divided by 4, is available on OSC2 with
pull-high resistor, which can be used to syn-
chronize external logic. The RC oscillator pro-
vides the most cost effective solution. However,
the frequency of the oscillation may vary with
VDD, temperature, and the chip itself due to
process variations. It is, therefore, not suitable
for timing sensitive operations where accurate
oscillator frequency is desired.
On the other hand, if the crystal oscillator is se-
lected, a crystal across OSC1 and OSC2 is
needed to provide the feedback and phase shift
requiredfortheoscillator,andnootherexternal
components are required. A resonator may be
connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but
two external capacitors in OSC1 and OSC2 are
needed.
There is another oscillator circuit designed for
the real time clock. In this case, only the
32.768kHzcrystaloscillatorcanbeapplied.The
crystal should be connected between OSC3 and
OSC4, and two external capacitors along with
one external resistor are required for the oscil-
lator circuit in order to get a stable frequency.
The RTC oscillator circuit can be controlled to
oscillate quickly by setting QOSC bit (bit 4 of
RTCC). It is recommended to turn on the quick
oscillating function upon power on, and turn it
off after two seconds.
The WDT oscillator is a free running on-chip
RC oscillator, and no external components are
required. Although the system enters the power
down mode, the system clock stops, and the
WDT oscillator still works with a period of ap-
proximately 78
s. The WDT oscillator can be
disabled by mask option to conserve power.
Watchdog timer
WDT
The WDT clock source is implemented by a ded-
icated RC oscillator (WDT oscillator) or an in-
struction clock (system clock/4) or a real time
clock oscillator (RTC oscillator). The timer is
designed to prevent a software malfunction or
sequence from jumping to an unknown location
with unpredictable results. The WDT can be
disabled by mask option. But if the WDT is dis-
abled, all executions related to the WDT lead to
no operation.
After the WDT clock source is selected, it
time-out period is fs/2
15
~fs/2
16
.
If the WDT clock source chooses the internal
WDT oscillator, the time-out period may vary
with temperature, VDD, and process varia-
tions. On the other hand, if the clock source se-
lects the instruction clock and the
instruction is executed, WDT may stop count-
ing and lose its protecting purpose, and the
logic can only be restarted by external logic.
halt
When the device operates in a noisy environ-
ment, using the on-chip RC oscillator (WDT
OSC) is strongly recommended, since the HALT
can stop the system clock.
The WDT overflow under normal operation
initializes a chip reset and sets the status bit
TO . In the HALT mode, the overflow
initializes a warm reset , and only the PC and
SP are reset to zero. To clear the contents of the
WDT, there are three methods to be adopted,
i.e., external reset (a low level to RES), software
instruction, and HALT instruction. There are
two sets of software instructions, CLR WDT
and the other set
CLR WDT1 and CLR
WDT2 . Of these two types of instructions, only
one type of instruction can be active at a time
depending on the mask option
CLR WDT
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Watchdog timer