HT48RA1/HT48CA1
Rev. 1.00
16
June 25, 2004
Timer/Event Counter 1 preload register. The
Timer/Event Counter 1 will still operate until the overflow
occurs (a Timer/Event Counter 1 reloading will occur at
the same time).
When the Timer/Event Counter 1 (reading TMR1H) is
read, the clock will be blocked to avoid errors. As this
may results in a counting error, this must be taken into
consideration by the programmer.
The definitions of the TMR1C are as shown.
(Label
Function
0~2 Unused bit, read as 0
T1E
3
TodefinetheactiveedgeofTMR1pin
input signal
(0/1:activeonlowtohigh/hightolow)
T1ON
4
To enable/disable timer 1 counting
(0/1: disabled/enabled)
5
Unused bit, read as 0
T1M0
T1M1
6
7
To define the operating mode (T1M1,
T1M0)
01=Eventcountmode(externalclock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C Register
Input/Output Ports
There are 23 bi-directional input/output lines in the mi-
cro-controller, labeled from PA to PC and PF, which are
mapped to the data memory of [12H], [14H], [16H] and
[1CH], respectively. All of these I/O ports can be used as
input and output operations. For input operation, these
ports are non-latching, that is, the inputs must be ready
at the T2 rising edge of instruction MOV A,[m] (m =
12H, 14H, 16H or 1CH). For output operation, all the
data is latched and remains unchanged until the output
latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PFC) to control the input/output configuration.
With this control register, CMOS output or Schmitt trig-
ger input with or without (depends on options) pull-high
resistorstructurescanbereconfigureddynamically(i.e.,
on-the fly) under software control. To function as an in-
put,thecorrespondinglatchofthecontrolregisterhasto
be set as 1 . The pull-high resistor (if the pull-high re-
sistor is enabled) will be exhibited automatically. The in-
put sources also depends on the control register. If the
control register bit is 1 , the input will read the pad state
( mov and read-modify-write instructions”). If the con-
trol register bit is 0, the contents of the latches will move
to internal data bus ( mov and read-modify-write in-
structions). The input paths (pad state or latches) of
read-modify-write instructions are dependent on the
control register bits. For output function, CMOS is the
only configuration. These control registers are mapped
to locations 13H, 15H, 17H and 1DH.
5
5
5
6
4 % ) " . 7
4 3
! ;
9 ( + 4
+ * , % )
4 # % 4
4
) " .
.
* ' 4 3
! ;
9 ( + 4 6
4 % ) " . 7
! / 4
! * ! 4
& , *
6
4 % ) " . 7
E
-
E
E
-
E
% ) * % " 4
, *
! * ! 4
(
3
, * 4
% ) * % " 4
& , *
1 , + 4
*
! / 4
% ) * % " 4
& , *
3
, * 4
! * ! 4
& , *
! * ! 4
, *
4 # % 4
4
) " . F 4
% ) * % " G
4
! * ! 4
& , *
Input/Output Ports