參數(shù)資料
型號: HT48R10A-1
廠商: Holtek Semiconductor Inc.
英文描述: 8-Bit High Performance RISC-like Microcontroller Suitable for Multiple I/O Application(高性能、指令類似RISC的8位微控制器,用于多I/O接口設(shè)備)
中文描述: 8位高性能RISC架構(gòu)微控制器等的多個I / O應(yīng)用(高性能,指令類似的RISC的8位微控制器,用于多予適用/輸出接口設(shè)備)
文件頁數(shù): 20/45頁
文件大?。?/td> 321K
代理商: HT48R10A-1
HT48R10A-1
20
November 29, 2000
ROM code option
The following table shows all kinds of ROM code option in the microcontroller. All of the ROM code
options must be defined to ensure proper system functioning.
Items
Option
1
WDT clock source: WDTOSC/f
TID
/RTCOSC/disable
2
CLRWDT instructions: 1 or 2 instructions
3
Timer/event counter clock sources: f
SYS
or RTCOSC
4
PA wake-up
5
PA CMOS/SCHMITT input
6
PA pull-high enable/disable
7
PB pull-high enable/disable
8
PC pull-high enable/disable
9
BZ/BZ enable/disable
10
LVR enable/disable
11
System oscillator
Ext.RC, Ext.crystal, Int.RC+RTC or Int.RC+PC3/PC4
12
Int.RC frequency selection 3.2MHz, 1.6MHz, 800kHz or 400kHz
PROM programming and verification
The
microcontroller is arranged into a 1024 14 bits
program memory and a 16 8 bits option mem-
ory. The program code and option code are
stored in the program and option memories.
The programming of memories can be summa-
rized in nine steps as described below:
program
memory
used
in
the
Power on (V
DD
=6.25V)
Set VPP (RES) to 12.5V
Set CS (PA5) to low
Let PA3~PA0 (AD3~AD0) be the address and
data bus and the PA4 (CLK) be the clock input.
The data on the AD3~AD0 pins will be clocked
into or out of the microcontroller on the falling
edge of PA4 (CLK) for OTP programming and
verification.
The address data contains the code address (11
bits) and two option bits. Acomplete write cycle
will contain four CLK cycles. The first cycle,
bits 0~3 of the address are latched into the de-
vice. The second and third cycles, bits 4~7 and
bits 8~9 are latched respectively. The fourth cy-
cle, bit 2 is the TSEL option bit and bit 3 is the
OSEL option bit. Bits 2~3 in the third cycle and
bits 0~1 in the fourth cycle are undefined. If the
TSEL is "1" and the OSEL is "0", the TEST
memory will be read. If the TSEL is "0" and the
OSEL is "1", the option memory will be ac-
cessed. If both the TSEL and OSEL are "0", the
program memory will be managed.
The code data is 14 bits wide. A complete
read/write cycle contains four CLK cycles. In
the first cycle, bits 0~3 of the code data are ac-
cessed. In the second and third, bits 4~7 and
bits 8~11 are accessed respectively. In the
fourth cycle, bits 12~13 are accessed. Bits
14~15 are undefined. During code verification,
reading will return the result "00".
Select the TSEL and OSEL to program and
verify the program memory and option mem-
ory. Use the R/W (PA6) to select between pro-
gramming or verification.
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