參數(shù)資料
型號: HT48CA0
廠商: Holtek Semiconductor Inc.
元件分類: 8位微控制器
英文描述: 8-BIT MICROCONTROLLER
中文描述: 8位微控制器
文件頁數(shù): 3/32頁
文件大?。?/td> 238K
代理商: HT48CA0
D.C. Characteristics
Ta=25 C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
V
DD
Operating Voltage
2.0
3.6
V
I
DD
Operating Current
3V
No load, f
SYS
=4MHz
0.7
1.5
mA
I
STB
Standby Current
3V
No load, system HALT
1
A
V
IL1
Input Low Voltage for I/O Ports
3V
0
0.3V
DD
V
V
IH1
Input High Voltage for I/O Ports
3V
0.7V
DD
V
DD
V
V
IL2
Input Low Voltage (RES)
3V
0
0.4V
DD
V
V
IH2
Input High Voltage (RES)
3V
0.9V
DD
V
DD
V
V
LVR
Low Voltage Reset Voltage
1.9
2.0
V
I
OL
I/O Ports Sink Current
3V
V
OL
=0.1V
DD
4
8
mA
I
OH
PC0/REM Output Source Current
3V
V
OH
=0.9V
DD
2
4
mA
R
PH
Pull-high Resistance
3V
20
60
100
k
A.C. Characteristics
Ta=25 C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
f
SYS
System Clock
3V
400
4000
kHz
t
RES
External Reset Low Pulse Width
1
s
t
SST
System Start-up Timer Period
Power-up,resetorwake-up
from HALT
1024
t
SYS
t
LVR
Low Voltage Width to Reset
1
ms
Note: t
SYS
=1/f
SYS
HT48RA0-2/HT48CA0-2
Rev. 1.50
3
July 23, 2004
Functional Description
Execution Flow
The HT48RA0-2/HT48CA0-2 system clock can be de-
rived from a crystal/ceramic resonator oscillator. It is in-
ternally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute within one cycle. If an instruc-
tion changes the program counter, two cycles are
required to complete the instruction.
2
*
2
*
2
*
,
! # 6
# 7
8
9
# 6
# 7
: 8
,
! # 6
# 7
;
8
9
# 6
# 7
8
,
! # 6
# 7
;
8
9
# 6
# 7
;
8
;
;
#
1
<
#
1
Execution Flow
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