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參數(shù)資料
| 型號： | HT46C63(100QFP) |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 4/42頁 |
| 文件大?。?/td> | 362K |
| 代理商： | HT46C63(100QFP) |
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Pad Assignment
HT46C63
* The IC substrate should be connected to VSS in the PCB layout artwork.
Pin Description
Pin Name
I/O
Option
Description
PA0~PA7
I/O
Pull-high
Wake-up
I/O lines with pull-high resistors (bit option). I/O modes of each line are con-
trolled by related control register bit (PAC). Each line of PA can be optioned
as a wake-up input (bit option). I/O configurations: Schmitt trigger/CMOS
PB0/AN0~
PB7/AN7
I/O
Pull-High
I/O lines with pull-high resistors (bit option). I/O modes of each line are con-
trolled by related control register bit (PBC). I/O configurations: Schmitt trig-
ger/CMOS. Each PB line is pin shared with an A/D converter input.
PC0~PC6
PC7
I/O
Pull-High
I/O lines with pull-high resistors (bit option). I/O modes of each line are con-
trolled by related control register bit (PCC). I/O configurations: Schmitt trig-
ger/CMOS.
PD0~PD3
PD4/INT0
PD5/INT1
PD6/TMR
PD7
I/O
Pull-High
PWM Interrupt
Falling and/or
Rising
I/O lines with pull-high resistors (bit option). I/O modes of each line are con-
trolled by related control register bit (PDC). I/O configurations: Schmitt trig-
ger/CMOS. The PD0~PD3 can be selected as PWM outputs. INT0/INT1
are falling/rising edge selectable triggers.
HT46R63/HT46C63
Rev. 1.00
4
September 9, 2002
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3
3
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4
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4 1
4 1
4 1
4 1
4 1
4 1
4 1
4 1
4 1
4 1 7
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4 1
4 1
4 1
7
4 1
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4 1
4 1
4 1
4 1
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5
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