參數(shù)資料
型號: HT27C020
廠商: Holtek Semiconductor Inc.
英文描述: OTP CMOS 256Kx 8-Bit EPROM
中文描述: 檢察官辦公室的CMOS 256Kx 8位存儲器
文件頁數(shù): 7/11頁
文件大?。?/td> 286K
代理商: HT27C020
to output (t
CE
). Data is available at the outputs
(t
OE
) after the falling edge of OE , assuming the
CE has been LOW and addresses have been
stable for at least t
ACC
-t
OE
.
Standby mode
The HT27C020 has CMOS standby mode which
reduces the maximum VCC current to 10
μ
A. It
is placed in CMOS standby when CE is at
V
CC
±
0.3V. The HT27C020 also has a TTL-
standby mode which reduces the maximum
VCC current to 1.0mA. It is placed in TTL-
standby when CE is at V
IH
. When in standby
mode, the outputs are in a high-impedance
state, independent of the OE input.
Two-line output control function
To accommodate multiple memory connections,
a two-line control function is provided to allow
for:
Low memory power dissipation
Assurance that output bus contention will not
occur
It is recommended that CE be decoded and used
as the primary device-selection function, while
OE be made a common connection to the READ
line from the system control bus. This assures
that all deselected memory devices are in their
low-power standby mode and that the output
pins are only active when data is desired from a
particular memory device.
System considerations
During the switch between active and standby
conditions, transient current peaks are pro-
duced on the rising and falling edges of Chip
E nable. The magnitude of these transient cur-
rent peaks is dependent on the output capaci-
tance loading of the device. At a minimum, a
0.1
μ
F ceramic capacitor (high frequency, low
inherent inductance) should be used on each
device between VCC and VPP to minimize tran-
sient effects. In addition, to overcome the volt-
age drop caused by the inductive effects of the
printed circuit board traces on E PROM arrays,
a 4.7
μ
F bulk electrolytic capacitor should be
used between VCC and VPP for each eight de-
vices. The location of the capacitor should be
close to where the power supply is connected to
the array.
Operation mode truth table
All the operation modes are shown in the table following.
Mode
CE
V
IL
V
IL
V
IH
OE
V
IL
V
IH
X
X
V
IH
V
IL
X
V
IL
V
IL
PGM
X (2)
X
X
X
V
IL
V
IH
X
X
X
A0
X
X
X
X
X
X
X
V
IL
V
IH
A1
X
X
X
X
X
X
X
V
IH
V
IH
A9
X
X
X
X
X
X
X
VPP
V
CC
V
CC
V
CC
V
CC
V
PP
V
PP
V
PP
V
CC
V
CC
Output
Dout
High Z
High Z
High Z
D
IN
D
OUT
High Z
1C
02
Read
Output Disable
Standby (TTL)
Standby (CMOS)
Program
Program Verify
Product Inhibit
Manufacturer Code (3)
Device Type Code (3)
V
CC
±
0.3V
V
IL
V
IL
V
IH
V
IL
V
IL
V
H
(1)
V
H
(1)
Notes: (1) V
H
= 12.0V
±
0.5V
(2) X=E ither V
IH
or V
IL
(3) For Manufacturer Code and Device Code, A1=V
IH
, When A1=V
IL
, both codes will read 7F
HT27C020
7
10th May ’99
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