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參數(shù)資料
| 型號： | HT27C010 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 128K x 8-Bit CMOS OTP EPROM(128K x 8位 CMOS一次可編程EPROM) |
| 中文描述： | 128K的× 8位檢察官辦公室的CMOS存儲器（128K的× 8位的CMOS一次可編程存儲器） |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 285K |
| 代理商： | HT27C010 |
to output (t
CE
). Data is available at the outputs
(t
OE
) after the falling edge of OE , assuming the
CE has been LOW and addresses have been
stable for at least t
ACC
-t
OE
.
Standby mode
The HT27C010 has CMOS standby mode which
reduces the maximum VCC current to 10
μ
A. It
is placed in CMOS standby when CE is at
V
CC
±
0.3V. The HT27C010 also has a TTL -
standby mode which reduces the maximum
VCC current to 1.0mA. It is placed in TTL-
standby when CE is at V
IH
. When in standby
mode, the outputs are in a high-impedance
state, independent of the OE input.
Two-line output control function
To accommodate multiple memory connections,
a two-line control function is provided to allow
for:
Low memory power dissipation
Assurance that output bus contention will not
occur
It is recommended that CE be decoded and used
as the primary device-selection function, while
OE be made a common connection to the READ
line from the system control bus. This assures
that all deselected memory devices are in their
low-power standby mode and that the output
pins are only active when data is desired from a
particular memory device.
System considerations
During the switch between active and standby
conditions, transient current peaks are pro-
duced on the rising and falling edges of Chip
E nable. The magnitude of these transient cur-
rent peaks is dependent on the output capaci-
tance loading of the device. At a minimum, a
0.1
μ
F ceramic capacitor (high frequency, low
inherent inductance) should be used on each
device between VCC and VPP to minimize tran-
sient effects. In addition, to overcome the volt-
age drop caused by the inductive effects of the
printed circuit board traces on E PROM arrays,
a 4.7
μ
F bulk electrolytic capacitor should be
used between VCC and VPP for each eight de-
vices. The location of the capacitor should be
close to where the power supply is connected to
the array.
Operation mode truth table
All the operation modes are shown in the table following.
Mode
CE
OE
PGM
A0
A1
A9
VPP
Output
Read
V
IL
V
IL
X (2)
X
X
X
V
CC
Dout
Output Disable
V
IL
V
IH
X
X
X
X
V
CC
High Z
Standby (TTL)
V
IH
X
X
X
X
X
V
CC
High Z
Standby (CMOS)
V
CC
±
0.3V
X
X
X
X
X
V
CC
High Z
Program
V
IL
V
IH
V
IL
X
X
X
V
PP
D
IN
Program Verify
V
IL
V
IL
V
IH
X
X
X
V
PP
D
OUT
Product Inhibit
V
IH
X
X
X
X
X
V
PP
High Z
Manufacturer Code (3)
V
IL
V
IL
X
V
IL
V
IH
V
H
(1)
V
CC
1C
Device Type Code (3)
V
IL
V
IL
X
V
IH
V
IH
V
H
(1)
V
CC
01
Notes: (1) V
H
=12.0V
±
0.5V
(2) X=E ither V
IH
or V
IL
(3) For Manufacturer Code and Device Code, A1=V
IH
, When A1=V
IL
, both
codes will read 7F
HT27C010
7
6th May ’99
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相關代理商/技術參數(shù) |
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|---|---|
| HT27C010-120(32DIP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
| HT27C010-120(32PLCC) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
| HT27C010-120(32SOP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
| HT27C010-70(32DIP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
| HT27C010-70(32PLCC) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
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