Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Programming the OTP ROM
f
SCK
SCK Frequency
48
70
160
kHz
t
WH
SCK High Time
3
7.5
10.5
s
t
WL
SCK Low Time
3
7.5
10.5
s
t
CS
Minimum CS High Time
2
s
t
CSS
CS Setup Time
2
s
t
CSH
CS Hold Time
2
s
t
SU
Data in Setup Time
100
ns
t
H
Data in Hold Time
100
ns
Note:
For normal READ operation, don t use the 99H instruction.
Test Waveforms and Measurements
Output Test Load
HT25LC512
Rev. 1.10
4
October 17, 2005
Functional Description
Device Operation
The HT25LC512 operation is controlled by instructions
from the host processor. The HT25LC512 has only 3
kinds of instructions, Memory Read, Status Register
read and Product ID Read. Any invalid instruction will
be ignored without response from the HT25LC512. A
valid instruction starts with the falling edge of CS fol-
lowed by the appropriate 8-bit opcode and the memory
address location. While the CS pin is low, toggling the
SCK pin controls the loading of the opcode and the
memory address location through the SI (serial input)
pin. All instructions, addresses and data are transferred
with the most significant bit (MSB) first.
Memory read
Reading the HT25LC512 via the SO (Serial Output)
pin requires the following sequence. After the CS line
is pulled low to select a device, the READ instruction
is transmitted via the SI line followed by the byte ad-
dress to read. Upon completion, any data on the SI
line will be ignored. The data (D7-D0) at the specified
addressisthenshiftedoutontotheSOline.Ifonlyone
byteistoberead,theCSlineshouldbedrivenhighaf-
ter the data comes out. The READ instruction can be
continued since the byte address is automatically in-
cremented and data will continue to be shifted out.
When the highest address is reached, the address
counterwillrollovertothelowestaddressallowingthe
entire memory to be read in one continuous READ in-
struction.
% - '
. - ' +
/
0
1
/
1
1
% - .
. - (
t
R
, t
F
< 5ns (10% to 90%)
1
& .
2
Memory read, bit sequence is shown as follows:
Bit Sequential
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit data
0
0
0
0
x
0
1
1
x
x
x
x
x
x
x
0
Bit Sequential
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Bit data
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Note:
x don t care