HT24LC16
Rev. 1.30
5
November 25, 2003
Current address read
The internal data word address counter maintains the
last address accessed during the last read or write op-
eration, incremented by one. This address stays valid
betweenoperationsaslongasthechippowerismain-
tained. The address roll over during read from the last
byteofthelastmemorypagetothefirstbyteofthefirst
page. The address roll over during write from the last
byte of the current page to the first byte of the same
page. Once the device address with the read/write se-
lect bit set to one is clocked in and acknowledged by
the EEPROM, the current address data word is seri-
ally clocked out. The microcontroller should respond
with a no ACK signal (high) followed by a stop condi-
tion (refer to Current read timing).
Random read
Arandom read requires a dummy byte write sequence
to load in the data word address which is then clocked
in and acknowledged by the EEPROM. The
microcontroller must then generate another start con-
dition. The microcontroller now initiates a current ad-
dress read by sending a device address with the
read/write select bit high. The EEPROM acknowl-
edges the device address and serially clocks out the
data word. The microcontroller should respond with a
no ACK signal (high) followed by a stop condition
(refer to Random read timing).
Sequential read
Sequential reads are initiated by either a current ad-
dress read or a random address read. After the
microcontroller receives a data word, it responds with
an acknowledgment. As long as the EEPROM re-
ceives an acknowledgment, it will continue to incre-
ment the data word address and serially clock out
sequential data words. When the memory address
limit is reached, the data word address will roll over
and the sequential read continues. The sequential
read operation is terminated when the microcontroller
responds with a no ACK signal (high) followed by a
stop condition.
2
) ( ! !
" "
! ) ( ! !
" "
4
.
(
4
3
)
4
4
5
2
) ( ! !
" "
(
Random Read Timing
2
) ( ! !
" "
5
4
.
(
3
)
4
Current Read Timing
2
) ( ! !
" "
5
)
.
(
4
4
5
) 6
5
) 6 7
3
)
4
Sequential Read Timing