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參數(shù)資料
| 型號： | HT2040A |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | Christmas Light Controller |
| 中文描述： | 圣誕節(jié)燈控制器 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 475K |
| 代理商： | HT2040A |
Pad Coordinates
Unit: mil
Pad No.
1
2
3
4
5
6
7
8
X
Y
Pad No.
9
10
11
12
13
14
15
16
X
Y
–46.47 –0.17
–46.47 –7.01
–46.47 –14.66
–46.47 –32.22
–46.47 –42.59
–34.74 –42.59
38.82 –42.59
46.47 –42.59
46.47 –23.89
46.47 –16.24
46.47
46.47
35.17
23.86
11.62
–0.32
–4.51
42.59
42.59
42.59
42.59
42.59
Chip size: 107
×
99 (mil)
2
* The IC substrate should be connected to VDD in the PCB layout artwork.
Pad Description
Pad No. Pad Name I/O
Internal
Connection
Description
1
L4
O
CMOS
Lamp driving signal
L4 generates a high SCR trigger signal to control the
lamp intensity.
2
VDD
I
—
Power supply (positive)
3
DK 1
I
CMOS
Pull-Low
Demo function or group-5 selection input
If MODE is connected to VSS or open, DK1 will enable
the demo mode, i.e., show all the configurations (group-
1 ~ group-10) by being momentarily connected to VDD.
If MODE is connected to VDD, group-5 will be shown by
connecting DK 1 to VDD.
4
SK 2
I
CMOS
Pull-Low
One key activated display or group-6 selection
If MODE is connected to VSS or floating, SK 2 will
display the next group by being momentarily pressed.
If MODE is connected to VDD, group-6 will be shown by
connecting SK2 to VDD.
5~8
K 3~K 6
I
CMOS
Pull-Low
Group1 ~ Group4 selection
If MODE is connected to VSS or floating, group-7~
group-10 will be shown by connecting MODE to VDD.
9
SYNC
I
CMOS
PLL synchronous signal input
The PLL circuit is synchronized to the AC power
supply. The system can operate with a 60Hz or 50Hz
AC power supply system.
10
C
I
NMOS
For low pass PLL filters
HT2040A
2
26th Mar ’97
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