
A.C. Characteristics
Ta=25 C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
t
PHL
Propagation Delay Time
5V
CLK
C
L
=15pF, R
L
=10k
DO
300
ns
t
PLH
5V
100
ns
t
r1
Rise Time
5V
C
L
=300pF, S0~S12
2
s
t
r2
5V
C
L
=300pF, G1~G16
0.5
s
t
f
Fall Time
5V
C
L
=300pF, Sn, Gn
120
s
t
max
Maximum Clock Frequency
5V
Duty=50%
1
MHz
C
i
Input Capacitance
5V
15
pF
t
CW
Clock Pulse Width
5V
400
ns
t
SW
Strobe Pulse Width
5V
1
us
t
SU
Data Setup Time
5V
100
ns
t
h
Data Hold Time
5V
100
ns
t
CS
Clock-Strobe Time
5V
CLK rising edge to CS rising edge
1
s
t
W
Wait Time
5V
CLKrisingedgetoCLKfallingedge
1
s
HT16511
Rev. 1.10
5
September 18, 2003
Functional Description
Display RAM and Display Mode
The static display RAM is organized into 40 8 bits and
stores the data transmitted from an external device to
the HT16511 through a serial interface. The contents of
the RAM are directly mapped to the contents of the VFD
driver. Data in the RAM can be accessed through the
data setting, address setting and display control com-
mands.Itisassignedaddressesin8-bitunitasfollows:
Note:
Only the lower 4 bits of the addresses assigned
to SEG17 through SEG20 are valid, the higher
4 bits are ignored.
Dimming Control
HT16511 provides 8-step dimmer function on display by
controlling the 3-bit binary command code. The full
pulse width of grid signal is divides into 16 uniform sec-
tions by PWM (pulse width modulation) technology.
The 16 uniform sections available form 8 steps dimmer
via 3-bit binary code. The 8-step dimmer includes 1/16,
2/16, 4/16, 10/16, 11/16, 12/16, 13/16 and 14/16. The
1/16 pulse width indicates minimum lightness. The
14/16 pulse width represents maximum lightness (Refer
to the display control command).
Key Matrix and Key-Input Data Storage RAM
The key matrix scans the series key states at each level
of the key strobe signal (S1/K1~S12/K12) output of the
HT16511. The key strobe signal outputs are
time-multiplexed signals from S1/K1~S12/K12. The
states of inputs K0~K3 are sampled by strobe signal
S1/K1~S12/K12 and latched into the register.
:
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