
7-74
Absolute Maximum Ratings
Thermal Information
5V Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.0V
9V Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11.0V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1, HBM
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to 70
o
C
Thermal Resistance (Typical, Note 1)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
θ
JA
(
o
C/W)
70
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
RCLK = 2.048MHz; MCLK = 25.6MHz; T
A
= 0
o
C to 70
o
C
PARAMETER
SYMBOL/PIN
MIN
TYP
MAX
UNIT
5V Supply Voltage
AVCC, DVCC
4.75
5.0
5.25
V
9V Supply Voltage
AVDD
8.55
9.0
9.45
V
5V Supply Current
I
AVCC
, I
DVCC
-
55
-
mA
DC
9V Supply Current
I
AVDD
-
60
-
mA
DC
Logical One Input Voltage
V
IH
3.325
-
-
V
Logical Zero Input Voltage
V
IL
-
-
1.575
V
Output High Voltage
V
OH
2.6
-
-
V
Output Low Voltage
V
OL
-
-
0.4
V
AC Electrical Specifications
AVCC, DVCC = +5V, AVDD = +9V; RCLK = 2.048MHz; MCLK = 25.6MHz;
T
A
= 0
o
C to 70
o
C
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
RESET Pulse Width
t
RES
500
-
-
ns
MCLK Period (25.6MHz)
t
MCP
-
39.1
-
ns
RCLK Period (2.048MHz)
t
RCP
-
488
-
ns
RCLK High
t
RCH
98
-
-
ns
RCLK Low
t
RCL
98
-
-
ns
CCLK Period (5MHz)
t
CCP
200
-
-
ns
CCLK High
t
CCH
150
-
-
ns
CCLK Low
t
CCL
150
-
-
ns
CDATA Setup to CCLK
t
CDS
50
-
-
ns
CDATA Hold from CCLK
t
CDH
-
-
50
ns
C_EN Strobe Edge to CCLK
t
CES
-100
-
100
ns
TXCLK Period (256kHz)
t
DCP
-
3910
-
ns
TXCLK High
t
DCH
195
-
-
ns
TXCLK Low
t
DCL
195
-
-
ns
TX_DATA Setup to TXCLK
t
DIS
150
-
-
ns
TX_DATA Hold from TXCLK
t
DIH
0
-
-
ns
HSP50307