參數(shù)資料
型號: HSP50016JC-75
廠商: INTERSIL CORP
元件分類: 數(shù)字信號處理外設(shè)
英文描述: Digital Down Converter
中文描述: 16-BIT, DSP-MIXER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 8/31頁
文件大小: 209K
代理商: HSP50016JC-75
3-205
In Up/down Chirp Mode, the phase accumulator is set to the
phase offset value and the minimum phase increment is
loaded into the Phase Increment Register. The delta phase
increment is added to the 24 LSBs of the Phase Increment
Register to form a new phase increment at each clock. The
phase increment is allowed to grow until it nears the
maximum phase increment value (as defined in the up chirp
description). The delta phase increment value is then
subtracted from the least significant bits of the Phase
Increment Register to form a new phase increment at each
clock. The phase increment is allowed to diminish until it
reaches the minimum phase increment value (as defined in
the down chirp description). The Phase Increment Register
is then reloaded with the minimum phase increment, and the
up/down cycle begins again. See Figure 6 for a graphical
representation of this process.
The minimum and maximum phase increments have
allowable values from 0 to 2
32
-1. This corresponds to the
phase increment:
FIGURE 5A. PHASE WORD DURING DOWN CHIRP
FIGURE 5B. DOWN CHIRP
FIGURE 6. UP/DOWN CHIRP
STARTING PHASE
+90
o
±
180
o
-90
o
0
o
(0)
(2)
(1)
(4)
(5)
θ
MAX INCR
-
θ
θ
MAX INCR
θ
OFFSET
(3)
θ
MAX INCR
-2
θ
θ
MAX INCR
-3
θ
MAX INCR
-4
θ
PHASE INCREMENT
TIME
PHASE
OFFSET
PHASE WORD
TIME
TIME
MAXIMUM
MINIMUM
COSINE OUTPUT OF SIN/COS GENERATOR
PHASE INCREMENT
TIME
PHASE WORD
TIME
TIME
MAXIMUM
MINIMUM
PHASE
OFFSET
COSINE OUTPUT OF SIN/COS GENERATOR
0
Phase Increment
π
1
(
2
32
)
radians
<
<
(EQ. 4)
HSP50016
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