參數(shù)資料
型號(hào): HSP50016-EV
廠商: Intersil Corporation
英文描述: DDC Evaluation Platform
中文描述: DDC的評(píng)估平臺(tái)
文件頁(yè)數(shù): 31/31頁(yè)
文件大?。?/td> 209K
代理商: HSP50016-EV
3-228
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
FIGURE 26. TIMING RELATIVE TO TCK
FIGURE 27. OUTPUT RISE AND FALL TIMES
Waveforms
(Continued)
ALL INPUTS
t
TCP
t
TH
t
TL
t
ATS
t
ATH
t
TRL
TRST
TDO, I, Q,
IQSTB, IQCLK
t
TOD
TCK
2.7V
2.3V
t
TOE
t
TDO
IQSTB, IQCLK
IQSTB, IQCLK
TDO, I, Q,
TDO, I, Q,
t
RF
t
RF
0.8V
2.0V
HSP50016
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