參數(shù)資料
型號: HSP48410
廠商: Intersil Corporation
英文描述: Histogrammer/Accumulating Buffer
中文描述: Histogrammer /累積緩沖區(qū)
文件頁數(shù): 11/12頁
文件大?。?/td> 84K
代理商: HSP48410
11
FCT0-2 Hold from LD
t
FH
t
SS
t
SH
t
PS
t
PH
t
LL
t
LS
t
WL
t
WH
t
AS
t
AH
t
WS
t
WH
t
RL
t
RH
t
RD
t
CY
t
OH
t
OE
t
OD
t
R
t
F
0
-
0
-
ns
START Setup to CLK
12
-
13
-
ns
START Hold from CLK
0
-
0
-
ns
PIN0-9 Setup Time
12
-
13
-
ns
PIN0-9 Hold Time
0
-
0
-
ns
LD Pulse Width
10
-
12
-
ns
LD Setup to START
Note 7
T
CP
12
T
CP
15
-
ns
WR Low
-
-
ns
WR High
12
-
15
-
ns
Address Setup
13
-
15
-
ns
Address Hold
1
-
1
-
ns
DIO Setup to WR
12
-
15
-
ns
DIO Hold from WR
1
-
1
-
ns
RD Low
35
-
43
-
ns
RD High
15
-
17
-
ns
RD Low to DIO Valid
-
35
-
43
ns
Read/Write Cycle Time
55
-
65
-
ns
DIO Valid after RD High
Note 8
-
0
-
0
ns
Output Enable Time
Note 9
-
18
-
19
ns
Output Disable Time
Note 8
-
18
-
19
ns
Output Rise Time
From 0.8V to 2.0V, Note 8
-
6
-
6
ns
Output Fall Time
From 2.0V to 0.8V, Note 8
-
6
-
6
ns
NOTES:
6. AC Testing is performed as follows: Input levels (CLK) 0.0V and 4.0V; input levels (all other inputs) 0V and 3.0V. Timing reference levels (CLK)
= 2.0V, (all others) = 1.5V. Output load circuit with C
L
= 40pF. Output transition measured at V
OH
1.5V and V
OL
1.5V.
7. There must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START.
8. Characterized upon initial design and after major changes to design and/or process.
9. Transition is measured at
±
200mV from steady state voltage with loading as specified in test load circuit with C
L
= 40pF.
AC Electrical Specifications
V
CC
= 5V
±
5%, T
A
= 0
o
C to 70
o
C (Note 6)
(Continued)
PARAMETER
SYMBOL
NOTES
-40 (40 MHz)
-33 (33 MHz)
UNITS
MIN
MAX
MIN
MAX
Test Load Circuit
EQUIVALENT CIRCUIT
C
L
IOH
1.5V
IOL
DUT
S
1
SWITCH S1 OPEN FOR I
CCSB
AND I
CCOP
±
INCLUDES STRAY AND JIG CAPACITANCE
HSP48410
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