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2
Pinouts
24 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T24
TOP VIEW
24 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F24
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
CSYNC
PCLK
AEN1
RDY1
READY
RDY2
AEN2
CLK
GND
CLK50
START
SLO/FST
16
17
18
19
20
21
22
23
24
15
14
13
V
DD
X1
X2
ASYNC
EFI
F/C
RES
S2/STOP
S1
S0
OSC
RESET
24
23
22
21
20
19
18
17
16
15
14
13
2
3
4
5
6
7
8
9
10
11
12
1
SLO/FST
CSYNC
PCLK
AEN1
RDY1
READY
RDY2
AEN2
CLK
GND
CLK50
START
V
DD
X1
X2
ASYNC
EFI
F/C
S0
S1
S2/STOP
RESET
RES
OSC
Pin Descriptions
PIN
PIN
NUMBER
TYPE
DESCRIPTION
X1
X2
23
22
I
O
CRYSTAL CONNECTIONS: X1 and X2 are the crystal oscillator connections. The crystal frequency
must be three times the maximum desired processor clock frequency. X1 is the oscillator circuit input and
X2 is the output of the oscillator circuit.
EFI
20
I
EXTERNAL FREQUENCY IN: When F/C is HIGH, CLK is generated from the EFI input signal. This input
signal should be a square wave with a frequency of three times the maximum desired CLK output
frequency.
F/C
19
I
FREQUENCY/CRYSTAL SELECT: F/C selects either the crystal oscillator or the EFI input as the main
frequency source. When F/C is LOW, the HS-82C85RH clocks are derived from the crystal oscillator
circuit. When F/C is HIGH, CLK is generated from the EFI input. F/C cannot be dynamically switched
during normal operation.
START
11
I
A low-to-high transition on START will restart the CLK, CLK50 and PCLK outputs after the appropriate
restart sequence is completed.
When in the crystal mode (F/C LOW) with the oscillator stopped, the oscillator will be restarted when a
Start command is received. The CLK, CLK50 and PCLK outputs will start after the oscillator input signal
(X1) reaches the Schmitt trigger input threshold and an 8K internal counter reaches terminal count. If F/C
is HIGH (EFI mode), CLK, CLK50 and PCLK will restart within 3 EFI cycles after START is recognized.
The HS-82C85RH will restart in the same mode (SLO/FST) in which it stopped. A high level on START
disables the STOP mode.
S0
S1
S2/STOP
13
14
15
I
I
I
S2/STOP, S1, S0 are used to stop the HS-82C85RH clock outputs (CLK, CLK50, PCLK) and are sampled
by the rising edge of CLK. CLK, CLK50 and PCLK are stopped by S2/STOP, S1, S0 being in the LHH
state on the low-to-high transition of CLK. This LHH state must follow a passive HHH state occurring on
the previous low-to-high CLK transition. CLK and CLK50 stop in the high state. PCLK stops in it’s current
state (high or low).
When in the crystal mode (F/C) low and a STOP command is issued, the HS-82C85RH oscillator will stop
along with the CLK, CLK50 and PCLK outputs. When in the EFI mode, only the CLK, CLK50 and PCLK
outputs will be halted. The oscillator circuit if operational, will continue to run. The oscillator and/or clock
is restarted by the START input signal going true (HIGH) or the reset input (RES) going low.
HS-82C85RH