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參數(shù)資料
| 型號(hào)： | HS7B-1145RH-Q |
| 廠(chǎng)商： | INTERSIL CORP |
| 元件分類(lèi)： | 音頻／視頻放大 |
| 英文描述： | Radiation Hardened, High Speed, Low Power, Current Feedback Video Operational Amplifier with Output Disable |
| 中文描述： | 1 CHANNEL, VIDEO AMPLIFIER, CDIP8 |
| 封裝： | SIDE BRAZED, DIP-8 |
| 文件頁(yè)數(shù)： | 3/9頁(yè) |
| 文件大?。?/td> | 145K |
| 代理商： | HS7B-1145RH-Q |
3
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (R
S
) in series with the output
prior to the capacitance.
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the R
S
and C
L
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
R
S
and C
L
form a low pass network at the output, thus
limiting system bandwidth well below the amplifier bandwidth
of 270MHz (for A
V
= +1). By decreasing R
S
as C
L
increases
(as illustrated in the curves), the maximum bandwidth is
obtained without sacrificing stability. In spite of this, the
bandwidth decreases as the load capacitance increases. For
example, at A
V
= +1, R
S
= 62
, C
L
= 40pF, the overall
bandwidth is limited to 180MHz, and bandwidth drops to
75MHz at A
V
= +1, R
S
= 8
, C
L
= 400pF.
Evaluation Board
The performance of the HS-1145RH may be evaluated using
the HFA11XX Evaluation Board.
The layout and schematic of the board are shown in Figure 2.
The V
H
connection may be used to exercise the DISABLE
pin, but note that this connection has no 50
termination. To
order evaluation boards (part number HFA11XXEVAL),
please contact your local sales office.
0
100
200
300
400
0
10
20
30
40
50
LOAD CAPACITANCE (pF)
S
)
A
V
= +1
150
250
350
50
FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs
LOAD CAPACITANCE
A
V
= +2
FIGURE 2A. TOP LAYOUT
FIGURE 2B. BOTTOM LAYOUT
FIGURE 2C. SCHEMATIC
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT
V
H
+IN
V
L
V+
GND
1
V-
OUT
1
2
3
4
8
7
6
5
+5V
10
μ
F
0.1
μ
F
V
H
50
GND
GND
R
1
-5V
0.1
μ
F
10
μ
F
50
IN
OUT
V
L
510
510
HS-1145RH
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