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參數(shù)資料
| 型號(hào)： | HS4-3182-8 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | ARINC 429 Bus Interface Line Driver Circuit |
| 中文描述： | LINE DRIVER, CQCC28 |
| 封裝： | CERAMIC, LCC-28 |
| 文件頁(yè)數(shù)： | 5/6頁(yè) |
| 文件大小： | 39K |
| 代理商： | HS4-3182-8 |
5-182
Driver Waveforms
NOTES: t
R
measured 50% to 90% times 2
t
F
measured 50% to 10% times 2
V
IH
= 5V
V
IL
= 0V
V
OL
= -4.75V to -5.25V
V
OH
= 4.75V to 5.25V
When the Data (A) input is in the Logic One state and the Data (B)
input is in the Logic Zero state, A
OUT
is equal to V
REF
and B
OUT
is
equal to -V
REF
. This constitutes the Output High state. Data (A) and
Data (B) both in the Logic Zero state causes both A
OUT
and B
OUT
to
be equal to 0V which designates the output Null state. Data (A) in
the Logic Zero state and Data (B) in the Logic One state causes
A
OUT
to be equal to -V
REF
and B
OUT
to be equal to V
REF
which is
the Output Low state.
Burn-In Schematic
NOTES: R = 400
±
5%
C
1
= 0.03
μ
F
±
20%
C
2
= C
3
= 500pF, NPO
+V = +15.5V
±
0.5V
-V = -15.5V
±
0.5V
V
1
= +5.5V
±
0.5V
A 0.0
μ
F decoupling capacitor is required on each of the three
supply lines (+V, -V and V
1
) at every 3rd Burn-In socket.
Ambient Temp. Max. = +125
o
C.
Package = 16 Lead Side Brazed DIP.
Pulse Conditions = A & B = 6.25kHz
±
10%. B is delayed one-half
cycle and in sync with A.
V
IH
= 2.0V Min.
V
IL
= 0.5V Max.
DATA (A) 0V
DATA (B) 0V
V
REF
A
OUT
0V
B
OUT
0V
t
PHL
-V
REF
A
OUT
- B
OUT
0V
DIFFERENTIAL
OUTPUT
50%
50%
50%
50%
t
PLH
t
R
t
F
2V
REF
-V
REF
V
REF
HIGH
NULL
LOW
-2V
REF
ADJ. BY
C
B
ADJ. BY
C
A
5V
0V
5V
0V
+4.75V TO +5.25V
-4.75V TO -5.25V
+4.75V TO +5.25V
-4.75V TO -5.25V
+9.5V TO +10.5V
NOTE: OUTPUTS UNLOADED
-9.5V TO -10.5V
V
1
DATA (B)
+V
C
1
GND
-V
DATA (A)
16
15
14
13
HS-3182
12
11
10
9
1
2
3
4
5
6
7
8
C
3
C
2
R
V
IL
V
IH
V
IH
V
IL
A
B
HS-3182
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