參數(shù)資料
型號: HS1-82C54RH-Q
廠商: HARRIS SEMICONDUCTOR
元件分類: XO, clock
英文描述: Radiation Hardened CMOS Programmable Interval Timer
中文描述: 3 TIMER(S), PROGRAMMABLE TIMER, CDIP24
文件頁數(shù): 2/21頁
文件大小: 171K
代理商: HS1-82C54RH-Q
949
HS-82C54RH
Pin Description
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
D7-D0
1-8
I/O
DATA: Bi-directional three state data bus lines, connected to system data bus.
CLK 0
9
I
CLOCK 0: Clock input of Counter 0.
OUT 0
10
O
OUT 0: Output of Counter 0.
GATE 0
11
I
GATE 0: Gate input of Counter 0.
GND
12
GROUND: Power supply connection.
OUT 1
13
O
OUT 1: Output of Counter 1.
GATE 1
14
I
GATE 1: Gate input of Counter 1.
CLK 1
15
I
CLOCK 1: Clock input of Counter 1.
GATE 2
16
I
GATE 2: Gate input of Counter 2.
OUT 2
17
O
OUT 2: Output of Counter 2.
CLK 2
18
I
CLOCK 2: Clock input of Counter 2.
A0, A1
19-20
I
ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write
operations. Normally connected to the system address bus.
A1
0
0
1
1
A0
0
1
0
1
Selects
Counter 0
Counter 1
Counter 2
Control Word Register
CS
21
I
CHIP SELECT: A low on this input enables the HS-82C54RH to respond to RD and WR signals.
RD and WR are ignored otherwise.
RD
22
I
READ: This input is low during CPU read operations.
WR
23
I
WRITE: This input is low during CPU write operations.
VDD
24
VDD: The +5V power supply pin. A 0.1
μ
F capacitor between pins 12 and 24 is recommended
for decoupling.
Functional Diagram
(8)
DATA
BUS
BUFFER
READ/
WRITE
LOGIC
CONTROL
WORD
REGISTER
D7-D0
RD
WR
A0
A1
CS
I
COUNTER
1
COUNTER
0
COUNTER
2
OUT 1
GATE 1
CLK 1
OUT 0
GATE 0
CLK 0
OUT 2
GATE 2
CLK 2
CONTROL
WORD
REGISTER
STATUS
LATCH
STATUS
REGISTER
CONTROL
LOGIC
OUT N
GATE N
CLK N
CRM
CRL
OLM
OLL
CE
INTERNAL BUS
Spec Number
518059
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