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參數(shù)資料
| 型號： | HS0-82C12RH-Q |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Radiation Hardened 8-Bit Input/Output Port |
| 中文描述： | 8 I/O, PIA-GENERAL PURPOSE, UUC24 |
| 封裝： | DIE-24 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大小： | 76K |
| 代理商： | HS0-82C12RH-Q |
4
Functional Description
Data Latch
The data latch is comprised of eight “D” type flip-flops. The
output of each flip-flop will follow the corresponding data
input (DI0 - DI7) when the clock (C) is high. The clock input
is level sensitive and the data becomes latched when the
clock returns low.
An asynchronous reset (CLR) is used to clear the latched
data. Since the clock (C) overrides the reset (CLR), the data
must be in the latched state in order to clear the flip-flops. If
the data is not latched (i.e. clock is high) when CLR goes
low, then the Q outputs of the data latch will continue to
follow the data input, overriding the reset signal.
Output Buffer
Three-state buffers are used to provide output drive for the
data latch. A high level on the “output buffer enable” control
line enables the buffer outputs. When “output buffer enable”
is low the buffer outputs are forced to the high-impedance
state.
Device Select Logic
The inputs DS1 and DS2 are used for device selection.
When DS1 is low and DS2 is high, the device is selected.
The output buffers are enabled and the service request flip-
flop is asynchronously cleared when the device is selected.
Mode
the mode input (MD) is used to control the state of the output
buffer and to determine the source of the data latch clock
(C). When MD is high, the output buffers are enabled and
the source of the data latch clock (C) is the device select
logic (DS1
DS2).
When MD is low, the state of the output buffer is controlled
by the device select logic (DS1
DS2) and the source of the
data latch clock is the strobe (STB) input.
Strobe
The strobe input (STB) is used as the data latch clock (C)
when the mode input (MD) is low. The service request flip-
flop is synchronously set on the negative going edge of STB.
Service Request Flip-Flop
The service request flip-flop is to generate interrupts to
microcomputer systems. It is negative edge triggered and
asynchronously cleared (reset).
The output of the service request flip-flop is AND-gated with
the device select logic (DS1
DS2). The output of the AND
gate is the active low interrupt (INT) signal.
HS-82C12RH
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