參數(shù)資料
型號(hào)： HS-80C86RH
廠商： HARRIS SEMICONDUCTOR
元件分類： 微控制器/微處理器
英文描述： Radiation Hardened 16-Bit CMOS Microprocessor
中文描述： 16-BIT, 5 MHz, MICROPROCESSOR, CDIP40
文件頁數(shù)： 7/37頁
文件大?。?/td> 239K
代理商： HS-80C86RH
862
Spec Number
518055
Specifications HS-80C86RH
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input or Output Voltage
Applied for all Grades. . . . . . . . . . . . . . . . . .VSS-0.3V to VDD+0.3V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65
o
C to +150
o
C
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300
o
C
Typical Derating Factor. . . . . . . . . . . 12mA/MHz Increase in IDDOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
SBDIP Package. . . . . . . . . . . . . . . . . . . .
Ceramic Flatpack Package . . . . . . . . . . .
Maximum Package Power Dissipation at +125
o
C Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.69W
If Device Power Exceeds Package Dissipation Capability, Provide
Heat Sinking or Derate Linearly at the Following Rate
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25.0mW/
o
C
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . .13.9mW/
o
C
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9750 Gates
θ
JA
θ
JC
40.0
o
C/W
72.1
o
C/W
8.6
o
C/W
9.7
o
C/W
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Supply Voltage Range (VDD) . . . . . . . +4.75V to +5.25V
Operating Temperature Range (T
A
) . . . . . . . . . . . . -35
o
C to +125
o
C
Input Low Voltage (VIL) . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . . . 3.5V to VDD
Clock Input Low Voltage (VILC) . . . . . . . . . . . . . . . . . . 0.0V to 0.8V
CLK and MN/MX Input High (VIHC) . . . . . . . . . .VDD - 0.8V to VDD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETERS
SYMBOL
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
-35
o
C, +25
o
C,
+125
o
C
-35
o
C, +25
o
C,
+125
o
C
-35
o
C, +25
o
C,
+125
o
C
-35
o
C, +25
o
C,
+125
o
C
LIMITS
UNITS
MIN
MAX
TTL High Level
Output Voltage
VOH1
VDD = 4.75V, IO = -2.5mA
VIN = 0V or VDD
1, 2, 3
3.0
-
V
CMOS High Level
Output Voltage
VOH2
VDD = 4.75V, IO = -100
μ
A
VIN = 0V or VDD
1, 2, 3
VDD -
0.4V
-
V
Low Level Output
Voltage
VOL
VDD = 4.75V, IO = +2.5mA
VIN = 0V or VDD
1, 2, 3
-
0.4
V
Input Leakage
Current
IIH or
IIL
VDD = 5.25V
VIN = 0V or VDD
Pins: 17-19, 21-23, 33
1, 2, 3
-1.0
1.0
μ
A
Output Leakage
Current
IOZL or
IOZH
VDD = 5.25V
VIN = 0V or VDD
Pins: 2-16, 26-29, 32, 34-39
1, 2, 3
-35
o
C, +25
o
C,
+125
o
C
-10
10
μ
A
Input Current Bus
Hold High
IBHH
VDD = 4.75V and 5.25V
VIN = 3.0V (Note 1)
Pins: 2-16, 26-32, 34-39
1, 2, 3
-35
o
C, +25
o
C,
+125
o
C
-600
-40
μ
A
Input Current Bus
Hold Low
IBHL
VDD = 4.75V and 5.25V
VIN = 0.8V (Note 2)
Pins: 2-16, 34-39
1, 2, 3
-35
o
C, +25
o
C,
+125
o
C
40
600
μ
A
Standby Power
Supply Current
IDDSB
VDD = 5.25V, VIN = GND or
VDD, IO = 0mA (Note 3)
1, 2, 3
-35
o
C, +25
o
C,
+125
o
C
-35
o
C, +25
o
C,
+125
o
C
-35
o
C, +25
o
C,
+125
o
C
-
500
μ
A
Operating Power
Supply Current
IDDOP
VDD = 5.25V, VIN = GND or
VDD, IO = 0mA, f = 1MHz
1, 2, 3
-
12
mA/MHz
Functional Tests
FT
VDD = 4.75V and 5.25V,
VIN = GND or VDD,
f = 1MHz
7, 8A, 8B
-
-
-
Noise Immunity
Functional Tests
FN
VDD = 4.75V and 5.25V,
VIN = GND or 3.5V and
VDD = 4.5V,
VIN = 0.8V or VDD (Note 4)
7, 8A, 8B
-35
o
C, +25
o
C,
+125
o
C
-
-
-
NOTES:
1. IBHH should be measured after raising VIN to VDD and then lowering to 3.0V.
2. IBHL should be measured after lowering VIN to VSS and then raising to 0.8V.
3. IDDSB tested during Clock high time after halt instruction executed.
4. CLK and MN/MX Input High (VIHC) = VDD -0.8
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