參數(shù)資料
型號(hào)： HS-80C85RH
廠商： HARRIS SEMICONDUCTOR
元件分類： 微控制器/微處理器
英文描述： Radiation Hardened 8-Bit CMOS Microprocessor
中文描述： 8-BIT, 2 MHz, MICROPROCESSOR, CDIP40
文件頁(yè)數(shù)： 11/19頁(yè)
文件大?。?/td> 159K
代理商： HS-80C85RH
11
HS-80C85RH
JPE
1
1
1
0
1
0
1
0
Jump on parity
even
JPO
1
1
1
0
0
0
1
0
Jump on parity odd
PCHL
1
1
1
0
1
0
0
1
H & L to program
counter
CALL
CALL
1
1
0
0
1
1
0
1
Call unconditional
CC
1
1
0
1
1
1
0
0
Call on carry
CNC
1
1
0
1
0
1
0
0
Call on no carry
LOGICAL
ANA r
1
0
1
0
0
S
S
S
And register with A
XRA r
1
0
1
0
1
S
S
S
Exclusive OR
register with A
ORA r
1
0
1
1
0
S
S
S
OR register with A
CMP r
1
0
1
1
1
S
S
S
Compare register
with A
ANA M
1
0
1
0
0
1
1
0
And memory with A
XRA M
1
0
1
0
1
1
1
0
Exclusive OR mem-
ory with A
ORA M
1
0
1
1
0
1
1
0
OR memory with A
CMP M
1
0
1
1
1
1
1
0
Compare memory
with A
ANI
1
1
1
0
0
1
1
0
And immediate
with A
XRI
1
1
1
0
1
1
1
0
Exclusive OR
immediate with A
ORl
1
1
1
1
0
1
1
0
OR immediate
with A
CPl
1
1
1
1
1
1
1
0
Compare immedi-
ate with A
ROTATE
RLC
0
0
0
0
0
1
1
1
Rotate A left
RRC
0
0
0
0
1
1
1
1
Rotate A right
RAL
0
0
0
1
0
1
1
1
Rotate A left
through carry
RAR
0
0
0
1
1
1
1
1
Rotate A right
through carry
INX H
0
0
1
0
0
0
1
1
Increment H & L
registers
DCX B
0
0
0
0
1
0
1
1
Decrement B & C
DCX D
0
0
0
1
1
0
1
1
Decrement D & E
DCX H
0
0
1
0
1
0
1
1
Decrement H & L
ADD
ADD r
1
0
0
0
0
S
S
S
Add register to A
ADC r
1
0
0
0
1
S
S
S
Add register to A
with carry
ADD M
1
0
C
0
0
1
1
0
Add memory to A
MNEMONIC
INSTRUCTION CODE
OPERATIONS
DESCRIPTION
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
ADC M
1
0
0
0
1
1
1
0
Add memory to A
with carry
ADl
1
1
0
0
0
1
1
0
Add immediate to A
ACl
1
1
0
0
1
1
1
0
Add immediate to A
with carry
DAD B
0
0
0
0
1
0
0
1
Add B & C to H & L
DAD D
0
0
0
1
1
0
0
1
Add D & E to H & L
DAD H
0
0
1
0
1
0
0
1
Add H & L to H & L
DAD SP
0
0
1
1
1
0
0
1
Add stack pointer to
H&L
SUBTRACT
SUB r
1
0
0
1
0
S
S
S
Subtract register
from A
SBB r
1
0
0
1
1
S
S
S
Subtract register
from A with borrow
SUB M
1
0
0
1
0
1
1
0
Subtract memory
from A
SBB M
1
0
0
1
1
1
1
0
Subtract memory
from A with borrow
SUl
1
1
0
1
0
1
1
0
Subtract immedi-
ate from A
SBl
1
1
0
1
1
1
1
0
Subtract immedi-
ate from A with
borrow
SPECIALS
CMA
0
0
1
0
1
1
1
1
Complement A
STC
0
0
1
1
0
1
1
1
Set carry
CMC
0
0
1
1
1
1
1
1
Complement carry
DAA
0
0
1
0
0
1
1
1
Decimal adjust A
CONTROL
El
1
1
1
1
1
0
1
1
Enable Interrupts
DI
1
1
1
1
0
0
1
1
Disable Interrupt
NOP
0
0
0
0
0
0
0
0
No-operation
HLT
0
1
1
1
0
1
1
0
Halt
RIM
0
0
1
0
0
0
0
0
Read Interrupt
Mask
SlM
0
0
1
1
0
0
0
0
Set Interrupt Mask
NOTES:
1. DDS or SSS: B000, C001, D010, E011, H100, L101, Memory 110, A111
2. Two possible cycle times (6/12) indicate instruction cycles dependent on condi-
tion flags.
All mnemonics copyrighted Intel Corporation 1976
MNEMONIC
INSTRUCTION CODE
OPERATIONS
DESCRIPTION
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
TABLE 9. INSTRUCTION SET SUMMARY (Continued)
Spec Number
518054
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