參數(shù)資料
型號(hào): HS-26C(T)32RH
廠商: Intersil Corporation
英文描述: ()
中文描述: ()
文件頁(yè)數(shù): 2/4頁(yè)
文件大?。?/td> 35K
代理商: HS-26C(T)32RH
4-2
FIGURE 2
.
N-channel source-follower high side drivers and NPN-based
output drivers have parasitic diodes which remain reverse-
biased with VDD at 0V and output voltages above ground.
These output types will not conduct until the E-B or S-B
diodes break down, typically above 7V.
The HS-26C31RH line driver is produced in a radiation hard-
ened CMOS process but uses a NPN bipolar output driver to
provide both high output drive and power-off output isolation.
The output can be run from ground to over 6V without signif-
icant leakage, with the supply off, unlike standard CMOS
logic types. This allows the outputs of active and inactive
drivers to be paralleled without complications.
The HS-26C32RH line receiver has an input structure which
provides a
±
10V maximum input signal range with respect to
device ground. The input impedance of the receiver is typi-
cally 10,000
, with no clamping devices at the pin. A pow-
ered-down device simply adds its input impedance in parallel
to the other devices on the line.
A curve tracer can demonstrate the difference in behavior
between a standard CMOS input and output with power off
and the HS-26C31/32RH devices’ line inputs and outputs.
The inactive CMOS devices clamp whatever line they are
attached to at less than a volt, drawing many milliamperes.
The line pins of the Intersil RS-422 chip set are well-
behaved, acting as a three-state output and a 10k
input.
FIGURE 3A.
FIGURE 3B.
FIGURE 3C.
FIGURE 3D.
FIGURE 3. PARASITIC DIODES FOR EACH OUTPUT
S (P)
D (P)
S (N)
D (N)
B (P)
S (N)
NMOS
PMOS
E (N)
B (P)
C/S (N)
NPN
S (N)
VDD
GND
M4
PMOS
M5
NMOS
S
STANDARD CMOS
OUTPUT STAGE
D11
D12
VDD UP
D10
D9
LINE
OK
FORWARD
BIASED
VO > 0V
VDD = GND
S
VDD
GND
GND
VDD
GND
M49
NMOS
M21
NMOS
S
NMOS ONLY
OUTPUT STAGE
D17
D50
VDD UP
D25
D55
LINE
OK
VDD = GND
S
GND
GND
GND
OK
VDD
GND
Q53
Q52
STANDARD LSTTL
OUTPUT STAGE
D31
D54
VDD UP
D28
D56
LINE
OK
VDD = GND
GND
OK
VDD
GND
Q58
INTERSIL BiCMOS
OUTPUT STAGE
D43
D59
VDD UP
D45
D57
LINE
OK
VDD = GND
GND
OK
M44
NMOS
S
Application Note 9520
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